108 lines
2.9 KiB
Diff
108 lines
2.9 KiB
Diff
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From 8bd1bb3a670aae791c4b2e9ab13c92768233368a Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Mon, 3 Feb 2014 09:51:43 +0800
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Subject: [PATCH] ARM: dts: sun6i: rename clock node names to clk@N
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Device tree naming conventions state that node names should match
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node function. Change fully functioning clock nodes to match and
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add clock-output-names to all sunxi clock nodes.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun6i-a31.dtsi | 19 ++++++++++++++-----
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1 file changed, 14 insertions(+), 5 deletions(-)
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--- a/arch/arm/boot/dts/sun6i-a31.dtsi
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+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
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@@ -70,17 +70,19 @@
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clock-frequency = <24000000>;
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};
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- osc32k: osc32k {
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+ osc32k: clk@0 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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+ clock-output-names = "osc32k";
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};
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- pll1: pll1@01c20000 {
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+ pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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+ clock-output-names = "pll1";
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};
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pll6: clk@01c20028 {
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@@ -103,6 +105,7 @@
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* Allwinner.
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*/
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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+ clock-output-names = "cpu";
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};
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axi: axi@01c20050 {
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@@ -110,6 +113,7 @@
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compatible = "allwinner,sun4i-axi-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&cpu>;
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+ clock-output-names = "axi";
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};
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ahb1_mux: ahb1_mux@01c20054 {
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@@ -117,6 +121,7 @@
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compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
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+ clock-output-names = "ahb1_mux";
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};
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ahb1: ahb1@01c20054 {
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@@ -124,9 +129,10 @@
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compatible = "allwinner,sun4i-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1_mux>;
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+ clock-output-names = "ahb1";
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};
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- ahb1_gates: ahb1_gates@01c20060 {
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+ ahb1_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
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reg = <0x01c20060 0x8>;
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@@ -152,9 +158,10 @@
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compatible = "allwinner,sun4i-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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+ clock-output-names = "apb1";
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};
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- apb1_gates: apb1_gates@01c20060 {
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+ apb1_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-apb1-gates-clk";
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reg = <0x01c20068 0x4>;
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@@ -169,6 +176,7 @@
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
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+ clock-output-names = "apb2_mux";
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};
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apb2: apb2@01c20058 {
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@@ -176,9 +184,10 @@
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compatible = "allwinner,sun6i-a31-apb2-div-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb2_mux>;
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+ clock-output-names = "apb2";
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};
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- apb2_gates: apb2_gates@01c2006c {
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+ apb2_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-apb2-gates-clk";
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reg = <0x01c2006c 0x4>;
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