65 lines
1.6 KiB
C
65 lines
1.6 KiB
C
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/*
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* BCM47XX Sonics SiliconBackplane embedded ram core
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*
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* Copyright 2006, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id: sbsocram.h,v 1.1.1.3 2006/02/27 03:43:16 honor Exp $
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*/
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#ifndef _SBSOCRAM_H
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#define _SBSOCRAM_H
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#define SR_COREINFO 0x00
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#define SR_BWALLOC 0x04
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#define SR_BISTSTAT 0x0c
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#define SR_BANKINDEX 0x10
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#define SR_BANKSTBYCTL 0x14
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#ifndef _LANGUAGE_ASSEMBLY
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/* Memcsocram core registers */
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typedef volatile struct sbsocramregs {
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uint32 coreinfo;
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uint32 bwalloc;
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uint32 PAD;
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uint32 biststat;
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uint32 bankidx;
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uint32 standbyctrl;
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} sbsocramregs_t;
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#endif
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/* Coreinfo register */
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#define SRCI_PT_MASK 0x30000
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#define SRCI_PT_SHIFT 16
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/* In corerev 0, the memory size is 2 to the power of the
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* base plus 16 plus to the contents of the memsize field plus 1.
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*/
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#define SRCI_MS0_MASK 0xf
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#define SR_MS0_BASE 16
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/*
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* In corerev 1 the bank size is 2 ^ the bank size field plus 14,
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* the memory size is number of banks times bank size.
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* The same applies to rom size.
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*/
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#define SRCI_ROMNB_MASK 0xf000
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#define SRCI_ROMNB_SHIFT 12
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#define SRCI_ROMBSZ_MASK 0xf00
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#define SRCI_ROMBSZ_SHIFT 8
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#define SRCI_SRNB_MASK 0xf0
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#define SRCI_SRNB_SHIFT 4
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#define SRCI_SRBSZ_MASK 0xf
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#define SRCI_SRBSZ_SHIFT 0
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#define SR_BSZ_BASE 14
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#endif /* _SBSOCRAM_H */
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