566 lines
15 KiB
C
566 lines
15 KiB
C
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/*
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* Synopsys Designware PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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/* Synopsis specific PCIE configuration registers */
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_MODE_MASK (0x3f << 16)
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#define PORT_LINK_MODE_1_LANES (0x1 << 16)
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#define PORT_LINK_MODE_2_LANES (0x3 << 16)
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#define PORT_LINK_MODE_4_LANES (0x7 << 16)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
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#define PCIE_MSI_ADDR_LO 0x820
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#define PCIE_MSI_ADDR_HI 0x824
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#define PCIE_MSI_INTR0_ENABLE 0x828
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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static struct hw_pci dw_pci;
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unsigned long global_io_offset;
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static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
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{
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return sys->private_data;
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}
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int cfg_read(void __iomem *addr, int where, int size, u32 *val)
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{
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*val = readl(addr);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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else if (size != 4)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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int cfg_write(void __iomem *addr, int where, int size, u32 val)
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{
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
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writew(val, addr + (where & 2));
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else if (size == 1)
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writeb(val, addr + (where & 3));
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
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{
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if (pp->ops->readl_rc)
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pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
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else
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*val = readl(pp->dbi_base + reg);
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}
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static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
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{
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if (pp->ops->writel_rc)
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pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
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else
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writel(val, pp->dbi_base + reg);
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}
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int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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int ret;
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if (pp->ops->rd_own_conf)
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ret = pp->ops->rd_own_conf(pp, where, size, val);
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else
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ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
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return ret;
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}
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int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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int ret;
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if (pp->ops->wr_own_conf)
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ret = pp->ops->wr_own_conf(pp, where, size, val);
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else
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ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
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val);
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return ret;
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}
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int dw_pcie_link_up(struct pcie_port *pp)
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{
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if (pp->ops->link_up)
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return pp->ops->link_up(pp);
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else
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return 0;
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}
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int __init dw_pcie_host_init(struct pcie_port *pp)
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{
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struct device_node *np = pp->dev->of_node;
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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u32 val;
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if (of_pci_range_parser_init(&parser, np)) {
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dev_err(pp->dev, "missing ranges property\n");
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return -EINVAL;
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}
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/* Get the I/O and memory ranges from DT */
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for_each_of_pci_range(&parser, &range) {
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unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
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if (restype == IORESOURCE_IO) {
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of_pci_range_to_resource(&range, np, &pp->io);
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pp->io.name = "I/O";
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pp->io.start = max_t(resource_size_t,
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PCIBIOS_MIN_IO,
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range.pci_addr + global_io_offset);
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pp->io.end = min_t(resource_size_t,
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IO_SPACE_LIMIT,
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range.pci_addr + range.size
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+ global_io_offset);
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pp->config.io_size = resource_size(&pp->io);
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pp->config.io_bus_addr = range.pci_addr;
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}
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if (restype == IORESOURCE_MEM) {
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of_pci_range_to_resource(&range, np, &pp->mem);
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pp->mem.name = "MEM";
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pp->config.mem_size = resource_size(&pp->mem);
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pp->config.mem_bus_addr = range.pci_addr;
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}
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if (restype == 0) {
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of_pci_range_to_resource(&range, np, &pp->cfg);
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pp->config.cfg0_size = resource_size(&pp->cfg)/2;
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pp->config.cfg1_size = resource_size(&pp->cfg)/2;
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}
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}
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if (!pp->dbi_base) {
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pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
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resource_size(&pp->cfg));
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if (!pp->dbi_base) {
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dev_err(pp->dev, "error with ioremap\n");
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return -ENOMEM;
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}
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}
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pp->cfg0_base = pp->cfg.start;
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pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
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pp->io_base = pp->io.start;
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pp->mem_base = pp->mem.start;
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pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
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pp->config.cfg0_size);
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if (!pp->va_cfg0_base) {
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dev_err(pp->dev, "error with ioremap in function\n");
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return -ENOMEM;
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}
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pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
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pp->config.cfg1_size);
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if (!pp->va_cfg1_base) {
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dev_err(pp->dev, "error with ioremap\n");
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return -ENOMEM;
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}
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if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
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dev_err(pp->dev, "Failed to parse the number of lanes\n");
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return -EINVAL;
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}
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if (pp->ops->host_init)
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pp->ops->host_init(pp);
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dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
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/* program correct class for RC */
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dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
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dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
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val |= PORT_LOGIC_SPEED_CHANGE;
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dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
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dw_pci.nr_controllers = 1;
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dw_pci.private_data = (void **)&pp;
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pci_common_init(&dw_pci);
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pci_assign_unassigned_resources();
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#ifdef CONFIG_PCI_DOMAINS
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dw_pci.domain++;
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#endif
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return 0;
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}
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static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
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{
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/* Program viewport 0 : OUTBOUND : CFG0 */
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dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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}
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static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
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{
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/* Program viewport 1 : OUTBOUND : CFG1 */
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dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
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}
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static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
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{
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/* Program viewport 0 : OUTBOUND : MEM */
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dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
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PCIE_ATU_UPPER_TARGET);
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}
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static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
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{
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/* Program viewport 1 : OUTBOUND : IO */
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dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
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dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
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dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
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PCIE_ATU_UPPER_TARGET);
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}
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static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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||
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{
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int ret = PCIBIOS_SUCCESSFUL;
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u32 address, busdev;
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|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
||
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
||
|
|
address = where & ~0x3;
|
||
|
|
|
||
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
||
|
|
dw_pcie_prog_viewport_cfg0(pp, busdev);
|
||
|
|
ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
|
||
|
|
dw_pcie_prog_viewport_mem_outbound(pp);
|
||
|
|
} else {
|
||
|
|
dw_pcie_prog_viewport_cfg1(pp, busdev);
|
||
|
|
ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
|
||
|
|
dw_pcie_prog_viewport_io_outbound(pp);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
||
|
|
u32 devfn, int where, int size, u32 val)
|
||
|
|
{
|
||
|
|
int ret = PCIBIOS_SUCCESSFUL;
|
||
|
|
u32 address, busdev;
|
||
|
|
|
||
|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
||
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
||
|
|
address = where & ~0x3;
|
||
|
|
|
||
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
||
|
|
dw_pcie_prog_viewport_cfg0(pp, busdev);
|
||
|
|
ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
|
||
|
|
dw_pcie_prog_viewport_mem_outbound(pp);
|
||
|
|
} else {
|
||
|
|
dw_pcie_prog_viewport_cfg1(pp, busdev);
|
||
|
|
ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
|
||
|
|
dw_pcie_prog_viewport_io_outbound(pp);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static int dw_pcie_valid_config(struct pcie_port *pp,
|
||
|
|
struct pci_bus *bus, int dev)
|
||
|
|
{
|
||
|
|
/* If there is no link, then there is no device */
|
||
|
|
if (bus->number != pp->root_bus_nr) {
|
||
|
|
if (!dw_pcie_link_up(pp))
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* access only one slot on each root port */
|
||
|
|
if (bus->number == pp->root_bus_nr && dev > 0)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* do not read more than one device on the bus directly attached
|
||
|
|
* to RC's (Virtual Bridge's) DS side.
|
||
|
|
*/
|
||
|
|
if (bus->primary == pp->root_bus_nr && dev > 0)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
||
|
|
int size, u32 *val)
|
||
|
|
{
|
||
|
|
struct pcie_port *pp = sys_to_pcie(bus->sysdata);
|
||
|
|
unsigned long flags;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (!pp) {
|
||
|
|
BUG();
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
|
||
|
|
*val = 0xffffffff;
|
||
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||
|
|
}
|
||
|
|
|
||
|
|
spin_lock_irqsave(&pp->conf_lock, flags);
|
||
|
|
if (bus->number != pp->root_bus_nr)
|
||
|
|
ret = dw_pcie_rd_other_conf(pp, bus, devfn,
|
||
|
|
where, size, val);
|
||
|
|
else
|
||
|
|
ret = dw_pcie_rd_own_conf(pp, where, size, val);
|
||
|
|
spin_unlock_irqrestore(&pp->conf_lock, flags);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
||
|
|
int where, int size, u32 val)
|
||
|
|
{
|
||
|
|
struct pcie_port *pp = sys_to_pcie(bus->sysdata);
|
||
|
|
unsigned long flags;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (!pp) {
|
||
|
|
BUG();
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
|
||
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
||
|
|
|
||
|
|
spin_lock_irqsave(&pp->conf_lock, flags);
|
||
|
|
if (bus->number != pp->root_bus_nr)
|
||
|
|
ret = dw_pcie_wr_other_conf(pp, bus, devfn,
|
||
|
|
where, size, val);
|
||
|
|
else
|
||
|
|
ret = dw_pcie_wr_own_conf(pp, where, size, val);
|
||
|
|
spin_unlock_irqrestore(&pp->conf_lock, flags);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct pci_ops dw_pcie_ops = {
|
||
|
|
.read = dw_pcie_rd_conf,
|
||
|
|
.write = dw_pcie_wr_conf,
|
||
|
|
};
|
||
|
|
|
||
|
|
int dw_pcie_setup(int nr, struct pci_sys_data *sys)
|
||
|
|
{
|
||
|
|
struct pcie_port *pp;
|
||
|
|
|
||
|
|
pp = sys_to_pcie(sys);
|
||
|
|
|
||
|
|
if (!pp)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
|
||
|
|
sys->io_offset = global_io_offset - pp->config.io_bus_addr;
|
||
|
|
pci_ioremap_io(sys->io_offset, pp->io.start);
|
||
|
|
global_io_offset += SZ_64K;
|
||
|
|
pci_add_resource_offset(&sys->resources, &pp->io,
|
||
|
|
sys->io_offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
|
||
|
|
pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
|
||
|
|
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
|
||
|
|
{
|
||
|
|
struct pci_bus *bus;
|
||
|
|
struct pcie_port *pp = sys_to_pcie(sys);
|
||
|
|
|
||
|
|
if (pp) {
|
||
|
|
pp->root_bus_nr = sys->busnr;
|
||
|
|
bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
|
||
|
|
sys, &sys->resources);
|
||
|
|
} else {
|
||
|
|
bus = NULL;
|
||
|
|
BUG();
|
||
|
|
}
|
||
|
|
|
||
|
|
return bus;
|
||
|
|
}
|
||
|
|
|
||
|
|
int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||
|
|
{
|
||
|
|
struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
|
||
|
|
|
||
|
|
return pp->irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct hw_pci dw_pci = {
|
||
|
|
.setup = dw_pcie_setup,
|
||
|
|
.scan = dw_pcie_scan_bus,
|
||
|
|
.map_irq = dw_pcie_map_irq,
|
||
|
|
};
|
||
|
|
|
||
|
|
void dw_pcie_setup_rc(struct pcie_port *pp)
|
||
|
|
{
|
||
|
|
struct pcie_port_info *config = &pp->config;
|
||
|
|
u32 val;
|
||
|
|
u32 membase;
|
||
|
|
u32 memlimit;
|
||
|
|
|
||
|
|
/* set the number of lines as 4 */
|
||
|
|
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
|
||
|
|
val &= ~PORT_LINK_MODE_MASK;
|
||
|
|
switch (pp->lanes) {
|
||
|
|
case 1:
|
||
|
|
val |= PORT_LINK_MODE_1_LANES;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
val |= PORT_LINK_MODE_2_LANES;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
val |= PORT_LINK_MODE_4_LANES;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
|
||
|
|
|
||
|
|
/* set link width speed control register */
|
||
|
|
dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
|
||
|
|
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
|
||
|
|
switch (pp->lanes) {
|
||
|
|
case 1:
|
||
|
|
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
|
||
|
|
|
||
|
|
/* setup RC BARs */
|
||
|
|
dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
|
||
|
|
dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
|
||
|
|
|
||
|
|
/* setup interrupt pins */
|
||
|
|
dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
|
||
|
|
val &= 0xffff00ff;
|
||
|
|
val |= 0x00000100;
|
||
|
|
dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
|
||
|
|
|
||
|
|
/* setup bus numbers */
|
||
|
|
dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
|
||
|
|
val &= 0xff000000;
|
||
|
|
val |= 0x00010100;
|
||
|
|
dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
|
||
|
|
|
||
|
|
/* setup memory base, memory limit */
|
||
|
|
membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
|
||
|
|
memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
|
||
|
|
val = memlimit | membase;
|
||
|
|
dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
|
||
|
|
|
||
|
|
/* setup command register */
|
||
|
|
dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
|
||
|
|
val &= 0xffff0000;
|
||
|
|
val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
||
|
|
PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
|
||
|
|
dw_pcie_writel_rc(pp, val, PCI_COMMAND);
|
||
|
|
}
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
|
||
|
|
MODULE_DESCRIPTION("Designware PCIe host controller driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|