2013-03-04 19:48:08 +08:00
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From 5e079d9b7ac5dda3be9f215f8440333597f57b26 Mon Sep 17 00:00:00 2001
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2013-02-22 01:47:15 +08:00
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From: Gabor Juhos <juhosg@openwrt.org>
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2013-03-04 19:48:08 +08:00
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Date: Sun, 3 Feb 2013 14:52:47 +0000
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Subject: [PATCH] MIPS: pci-ar724x: setup command register of the PCI
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controller
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commit 12401fc28d40aa5bf8bda6991a96b6d7a3dae3ac upstream.
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The command register of the PCI controller is
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not initialized correctly by the bootloader on
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some boards and this leads to non working PCI
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bus.
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Add code to initialize the command register
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from the Linux code to avoid this.
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2013-02-22 01:47:15 +08:00
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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2013-03-04 19:48:08 +08:00
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Patchwork: http://patchwork.linux-mips.org/patch/4916/
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Signed-off-by: John Crispin <blogic@openwrt.org>
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2013-02-22 01:47:15 +08:00
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---
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arch/mips/ath79/pci.c | 10 +++-
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 +
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arch/mips/pci/pci-ar724x.c | 63 ++++++++++++++++++++++++
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2013-03-04 19:48:08 +08:00
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3 files changed, 74 insertions(+), 1 deletion(-)
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2013-02-22 01:47:15 +08:00
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--- a/arch/mips/ath79/pci.c
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+++ b/arch/mips/ath79/pci.c
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2013-03-04 19:48:08 +08:00
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@@ -139,13 +139,14 @@ static struct platform_device *
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2013-02-22 01:47:15 +08:00
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ath79_register_pci_ar724x(int id,
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unsigned long cfg_base,
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unsigned long ctrl_base,
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+ unsigned long crp_base,
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unsigned long mem_base,
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unsigned long mem_size,
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unsigned long io_base,
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int irq)
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{
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struct platform_device *pdev;
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- struct resource res[5];
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+ struct resource res[6];
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memset(res, 0, sizeof(res));
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2013-03-04 19:48:08 +08:00
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@@ -173,6 +174,11 @@ ath79_register_pci_ar724x(int id,
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2013-02-22 01:47:15 +08:00
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res[4].start = io_base;
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res[4].end = io_base;
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+ res[5].name = "crp_base";
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+ res[5].flags = IORESOURCE_MEM;
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+ res[5].start = crp_base;
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+ res[5].end = crp_base + AR724X_PCI_CRP_SIZE - 1;
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+
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pdev = platform_device_register_simple("ar724x-pci", id,
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res, ARRAY_SIZE(res));
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return pdev;
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2013-03-04 19:48:08 +08:00
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@@ -188,6 +194,7 @@ int __init ath79_register_pci(void)
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2013-02-22 01:47:15 +08:00
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pdev = ath79_register_pci_ar724x(-1,
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AR724X_PCI_CFG_BASE,
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AR724X_PCI_CTRL_BASE,
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+ AR724X_PCI_CRP_BASE,
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AR724X_PCI_MEM_BASE,
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AR724X_PCI_MEM_SIZE,
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0,
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2013-03-04 19:48:08 +08:00
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@@ -203,6 +210,7 @@ int __init ath79_register_pci(void)
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2013-02-22 01:47:15 +08:00
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pdev = ath79_register_pci_ar724x(-1,
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AR724X_PCI_CFG_BASE,
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AR724X_PCI_CTRL_BASE,
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+ AR724X_PCI_CRP_BASE,
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AR724X_PCI_MEM_BASE,
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AR724X_PCI_MEM_SIZE,
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0,
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -67,6 +67,8 @@
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#define AR724X_PCI_CFG_BASE 0x14000000
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#define AR724X_PCI_CFG_SIZE 0x1000
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+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000)
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+#define AR724X_PCI_CRP_SIZE 0x1000
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#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000)
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#define AR724X_PCI_CTRL_SIZE 0x100
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -29,9 +29,17 @@
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#define AR7240_BAR0_WAR_VALUE 0xffff
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+#define AR724X_PCI_CMD_INIT (PCI_COMMAND_MEMORY | \
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+ PCI_COMMAND_MASTER | \
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+ PCI_COMMAND_INVALIDATE | \
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+ PCI_COMMAND_PARITY | \
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+ PCI_COMMAND_SERR | \
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+ PCI_COMMAND_FAST_BACK)
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+
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struct ar724x_pci_controller {
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void __iomem *devcfg_base;
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void __iomem *ctrl_base;
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+ void __iomem *crp_base;
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int irq;
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int irq_base;
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@@ -64,6 +72,51 @@ pci_bus_to_ar724x_controller(struct pci_
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return container_of(hose, struct ar724x_pci_controller, pci_controller);
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}
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+static int ar724x_pci_local_write(struct ar724x_pci_controller *apc,
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+ int where, int size, u32 value)
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+{
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+ unsigned long flags;
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+ void __iomem *base;
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+ u32 data;
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+ int s;
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+
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+ WARN_ON(where & (size - 1));
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+
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+ if (!apc->link_up)
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ base = apc->crp_base;
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+
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+ spin_lock_irqsave(&apc->lock, flags);
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+ data = __raw_readl(base + (where & ~3));
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+
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+ switch (size) {
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+ case 1:
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+ s = ((where & 3) * 8);
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+ data &= ~(0xff << s);
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+ data |= ((value & 0xff) << s);
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+ break;
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+ case 2:
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+ s = ((where & 2) * 8);
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+ data &= ~(0xffff << s);
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+ data |= ((value & 0xffff) << s);
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+ break;
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+ case 4:
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+ data = value;
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+ break;
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+ default:
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+ spin_unlock_irqrestore(&apc->lock, flags);
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+ return PCIBIOS_BAD_REGISTER_NUMBER;
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+ }
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+
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+ __raw_writel(data, base + (where & ~3));
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+ /* flush write */
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+ __raw_readl(base + (where & ~3));
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+ spin_unlock_irqrestore(&apc->lock, flags);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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@@ -324,6 +377,14 @@ static int ar724x_pci_probe(struct platf
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if (!apc->devcfg_base)
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return -EBUSY;
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crp_base");
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+ if (!res)
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+ return -EINVAL;
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+
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+ apc->crp_base = devm_request_and_ioremap(&pdev->dev, res);
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+ if (apc->crp_base == NULL)
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+ return -EBUSY;
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+
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apc->irq = platform_get_irq(pdev, 0);
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if (apc->irq < 0)
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return -EINVAL;
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@@ -360,6 +421,8 @@ static int ar724x_pci_probe(struct platf
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ar724x_pci_irq_init(apc, id);
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+ ar724x_pci_local_write(apc, PCI_COMMAND, 4, AR724X_PCI_CMD_INIT);
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+
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register_pci_controller(&apc->pci_controller);
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return 0;
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