2013-11-15 20:23:17 +08:00
|
|
|
On OMAP we have co-processor IPs, memory controllers,
|
|
|
|
|
GPIOs which control regulators and power switches to
|
|
|
|
|
PMIC, and SoC internal Bus IPs, some or most of which
|
|
|
|
|
should either not be reset or idled or both at init.
|
|
|
|
|
(In some cases there are erratas which prevent an IP
|
|
|
|
|
from being reset)
|
|
|
|
|
Have a way to pass this information from DT.
|
|
|
|
|
|
|
|
|
|
Update the am33xx/omap4 and omap5 dtsi files with the
|
|
|
|
|
new bindings for modules which either should not be
|
|
|
|
|
idled. reset or both. A later patch would cleanup the
|
|
|
|
|
same information that exists today as part of the hwmod
|
|
|
|
|
data files.
|
|
|
|
|
|
|
|
|
|
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
|
|
|
|
|
|
|
|
|
|
---
|
|
|
|
|
.../devicetree/bindings/arm/omap/omap.txt | 3 ++-
|
|
|
|
|
arch/arm/boot/dts/am33xx.dtsi | 2 ++
|
|
|
|
|
arch/arm/boot/dts/omap4.dtsi | 3 +++
|
|
|
|
|
arch/arm/boot/dts/omap5.dtsi | 2 ++
|
|
|
|
|
4 files changed, 9 insertions(+), 1 deletion(-)
|
|
|
|
|
|
|
|
|
|
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
|
|
|
|
|
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
|
|
|
|
|
@@ -21,7 +21,8 @@ Required properties:
|
|
|
|
|
Optional properties:
|
|
|
|
|
- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
|
|
|
|
|
during suspend.
|
|
|
|
|
-
|
|
|
|
|
+- ti,no-reset-on-init: When present, the module should not be reset at init
|
|
|
|
|
+- ti,no-idle-on-init: When present, the module should not be idled at init
|
|
|
|
|
|
|
|
|
|
Example:
|
|
|
|
|
|
|
|
|
|
--- a/arch/arm/boot/dts/am33xx.dtsi
|
|
|
|
|
+++ b/arch/arm/boot/dts/am33xx.dtsi
|
2013-11-27 20:34:41 +08:00
|
|
|
@@ -667,6 +667,7 @@
|
2013-11-15 20:23:17 +08:00
|
|
|
reg = <0x44d00000 0x4000 /* M3 UMEM */
|
|
|
|
|
0x44d80000 0x2000>; /* M3 DMEM */
|
|
|
|
|
ti,hwmods = "wkup_m3";
|
|
|
|
|
+ ti,no-reset-on-init;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
elm: elm@48080000 {
|
2013-11-27 20:34:41 +08:00
|
|
|
@@ -697,6 +698,7 @@
|
2013-11-15 20:23:17 +08:00
|
|
|
gpmc: gpmc@50000000 {
|
|
|
|
|
compatible = "ti,am3352-gpmc";
|
|
|
|
|
ti,hwmods = "gpmc";
|
|
|
|
|
+ ti,no-idle-on-init;
|
|
|
|
|
reg = <0x50000000 0x2000>;
|
|
|
|
|
interrupts = <100>;
|
|
|
|
|
gpmc,num-cs = <7>;
|
|
|
|
|
--- a/arch/arm/boot/dts/omap4.dtsi
|
|
|
|
|
+++ b/arch/arm/boot/dts/omap4.dtsi
|
|
|
|
|
@@ -214,6 +214,7 @@
|
|
|
|
|
gpmc,num-cs = <8>;
|
|
|
|
|
gpmc,num-waitpins = <4>;
|
|
|
|
|
ti,hwmods = "gpmc";
|
|
|
|
|
+ ti,no-idle-on-init;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart1: serial@4806a000 {
|
|
|
|
|
@@ -492,6 +493,7 @@
|
|
|
|
|
reg = <0x4c000000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "emif1";
|
|
|
|
|
+ ti,no-idle-on-init;
|
|
|
|
|
phy-type = <1>;
|
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
@@ -503,6 +505,7 @@
|
|
|
|
|
reg = <0x4d000000 0x100>;
|
|
|
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "emif2";
|
|
|
|
|
+ ti,no-idle-on-init;
|
|
|
|
|
phy-type = <1>;
|
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
--- a/arch/arm/boot/dts/omap5.dtsi
|
|
|
|
|
+++ b/arch/arm/boot/dts/omap5.dtsi
|
|
|
|
|
@@ -607,6 +607,7 @@
|
|
|
|
|
emif1: emif@0x4c000000 {
|
|
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif1";
|
|
|
|
|
+ ti,no-idle-on-init;
|
|
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4c000000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
@@ -618,6 +619,7 @@
|
|
|
|
|
emif2: emif@0x4d000000 {
|
|
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif2";
|
|
|
|
|
+ ti,no-idle-on-init;
|
|
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4d000000 0x400>;
|
|
|
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
