107 lines
2.9 KiB
Diff
107 lines
2.9 KiB
Diff
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From 43334f8438704001deb258b6e7223699bd336c77 Mon Sep 17 00:00:00 2001
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From: "Steven J. Hill" <Steven.Hill@imgtec.com>
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Date: Wed, 25 Sep 2013 14:58:19 -0500
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Subject: [PATCH 093/105] MIPS: GIC: Send IPIs using the GIC.
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If a GIC present, then use it to send IPIs between the cores.
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Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
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---
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arch/mips/kernel/smp-mt.c | 32 ++++++++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
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index 2f8c468..d057c84 100644
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--- a/arch/mips/kernel/smp-mt.c
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+++ b/arch/mips/kernel/smp-mt.c
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@@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
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/* Record this as available CPU */
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set_cpu_possible(tc, true);
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+ set_cpu_present(tc, true);
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__cpu_number_map[tc] = ++ncpu;
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__cpu_logical_map[ncpu] = tc;
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}
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@@ -112,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
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write_tc_c0_tchalt(TCHALT_H);
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}
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+static void mp_send_ipi_single(int cpu, unsigned int action)
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+{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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+
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+ switch (action) {
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+ case SMP_CALL_FUNCTION:
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+ gic_send_ipi(plat_ipi_call_int_xlate(cpu));
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+ break;
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+
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+ case SMP_RESCHEDULE_YOURSELF:
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+ gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
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+ break;
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+ }
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+
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+ local_irq_restore(flags);
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+}
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+
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static void vsmp_send_ipi_single(int cpu, unsigned int action)
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{
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int i;
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unsigned long flags;
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int vpflags;
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+ if (gic_present) {
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+ mp_send_ipi_single(cpu, action);
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+ return;
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+ }
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local_irq_save(flags);
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vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
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@@ -164,6 +188,8 @@ static void __cpuinit vsmp_init_secondary(void)
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static void __cpuinit vsmp_smp_finish(void)
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{
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+ pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id());
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+
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/* CDFIXME: remove this? */
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write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
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@@ -178,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(void)
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static void vsmp_cpus_done(void)
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{
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+ pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id());
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}
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/*
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@@ -191,6 +218,8 @@ static void vsmp_cpus_done(void)
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static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
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{
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struct thread_info *gp = task_thread_info(idle);
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+ pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n",
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+ smp_processor_id(), cpu);
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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@@ -232,6 +261,7 @@ static void __init vsmp_smp_setup(void)
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unsigned int mvpconf0, ntc, tc, ncpu = 0;
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unsigned int nvpe;
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+ pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id());
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* If we have an FPU, enroll ourselves in the FPU-full mask */
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if (cpu_has_fpu)
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@@ -272,6 +302,8 @@ static void __init vsmp_smp_setup(void)
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static void __init vsmp_prepare_cpus(unsigned int max_cpus)
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{
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+ pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n",
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+ smp_processor_id(), max_cpus);
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mips_mt_set_cpuoptions();
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}
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--
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1.7.10.4
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