2014-08-30 17:32:58 +08:00
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From 7456451e9df88d4c33479e3d4ea124d8a91ceb57 Mon Sep 17 00:00:00 2001
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From: Kumar Gala <galak@codeaurora.org>
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Date: Fri, 4 Apr 2014 11:32:56 -0500
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Subject: [PATCH 080/182] clk: qcom: Various fixes for MSM8960's global clock
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controller
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* Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs
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* Fix incorrect offset for PMIC_SSBI2_RESET
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* Fix typo:
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SIC_TIC -> SPS_TIC_H
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SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK
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* Fix naming convention:
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SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK
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SATA_SRC_CLK -> SATA_CLK_SRC
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Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Mike Turquette <mturquette@linaro.org>
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---
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drivers/clk/qcom/gcc-msm8960.c | 4 ++--
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include/dt-bindings/clock/qcom,gcc-msm8960.h | 7 +++----
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include/dt-bindings/reset/qcom,gcc-msm8960.h | 2 +-
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3 files changed, 6 insertions(+), 7 deletions(-)
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--- a/drivers/clk/qcom/gcc-msm8960.c
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+++ b/drivers/clk/qcom/gcc-msm8960.c
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2014-09-11 05:40:19 +08:00
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@@ -2810,7 +2810,7 @@ static const struct qcom_reset_map gcc_m
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2014-08-30 17:32:58 +08:00
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[PPSS_PROC_RESET] = { 0x2594, 1 },
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[PPSS_RESET] = { 0x2594},
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[DMA_BAM_RESET] = { 0x25c0, 7 },
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- [SIC_TIC_RESET] = { 0x2600, 7 },
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+ [SPS_TIC_H_RESET] = { 0x2600, 7 },
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[SLIMBUS_H_RESET] = { 0x2620, 7 },
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[SFAB_CFPB_M_RESET] = { 0x2680, 7 },
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[SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
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2014-09-11 05:40:19 +08:00
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@@ -2823,7 +2823,7 @@ static const struct qcom_reset_map gcc_m
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2014-08-30 17:32:58 +08:00
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[SFAB_SFPB_M_RESET] = { 0x2780, 7 },
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[SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
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[RPM_PROC_RESET] = { 0x27c0, 7 },
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- [PMIC_SSBI2_RESET] = { 0x270c, 12 },
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+ [PMIC_SSBI2_RESET] = { 0x280c, 12 },
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[SDC1_RESET] = { 0x2830 },
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[SDC2_RESET] = { 0x2850 },
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[SDC3_RESET] = { 0x2870 },
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--- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
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+++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
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@@ -51,7 +51,7 @@
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#define QDSS_TSCTR_CLK 34
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#define SFAB_ADM0_M0_A_CLK 35
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#define SFAB_ADM0_M1_A_CLK 36
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-#define SFAB_ADM0_M2_A_CLK 37
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+#define SFAB_ADM0_M2_H_CLK 37
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#define ADM0_CLK 38
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#define ADM0_PBUS_CLK 39
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#define MSS_XPU_CLK 40
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@@ -99,7 +99,7 @@
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#define CFPB2_H_CLK 82
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#define SFAB_CFPB_M_H_CLK 83
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#define CFPB_MASTER_H_CLK 84
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-#define SFAB_CFPB_S_HCLK 85
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+#define SFAB_CFPB_S_H_CLK 85
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#define CFPB_SPLITTER_H_CLK 86
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#define TSIF_H_CLK 87
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#define TSIF_INACTIVITY_TIMERS_CLK 88
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@@ -110,7 +110,6 @@
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#define CE1_SLEEP_CLK 93
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#define CE2_H_CLK 94
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#define CE2_CORE_CLK 95
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-#define CE2_SLEEP_CLK 96
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#define SFPB_H_CLK_SRC 97
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#define SFPB_H_CLK 98
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#define SFAB_SFPB_M_H_CLK 99
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@@ -252,7 +251,7 @@
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#define MSS_S_H_CLK 235
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#define MSS_CXO_SRC_CLK 236
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#define SATA_H_CLK 237
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-#define SATA_SRC_CLK 238
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+#define SATA_CLK_SRC 238
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#define SATA_RXOOB_CLK 239
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#define SATA_PMALIVE_CLK 240
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#define SATA_PHY_REF_CLK 241
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--- a/include/dt-bindings/reset/qcom,gcc-msm8960.h
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+++ b/include/dt-bindings/reset/qcom,gcc-msm8960.h
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@@ -58,7 +58,7 @@
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#define PPSS_PROC_RESET 41
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#define PPSS_RESET 42
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#define DMA_BAM_RESET 43
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-#define SIC_TIC_RESET 44
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+#define SPS_TIC_H_RESET 44
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#define SLIMBUS_H_RESET 45
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#define SFAB_CFPB_M_RESET 46
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#define SFAB_CFPB_S_RESET 47
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