rewrite of memory detection code, should be fix #1909
SVN-Revision: 7819
This commit is contained in:
Gabor Juhos
parent
e0f225831f
commit
0f6020d171
@ -15,6 +15,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/string.h>
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <asm/addrspace.h>
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@ -22,6 +23,7 @@
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_switch.h>
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#include <asm/mach-adm5120/adm5120_mpmc.h>
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#include <asm/mach-adm5120/adm5120_info.h>
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#include <asm/mach-adm5120/myloader.h>
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#include <asm/mach-adm5120/routerboot.h>
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@ -32,6 +34,8 @@ extern char *prom_getenv(char *envname);
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* Globals
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*/
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struct adm5120_board adm5120_board;
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EXPORT_SYMBOL_GPL(adm5120_board);
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unsigned int adm5120_boot_loader;
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unsigned int adm5120_product_code;
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@ -81,6 +85,7 @@ static struct adm5120_board __initdata adm5120_boards[] = {
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.mach_type = MACH_ADM5120_CAS771,
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.has_usb = 0,
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.iface_num = 5,
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.mem_size = (32 << 20),
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.flash0_size = 4*1024*1024,
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},
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{
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@ -137,6 +142,7 @@ static struct adm5120_board __initdata adm5120_boards[] = {
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.mach_type = MACH_ADM5120_WP54AG,
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.has_usb = 0,
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.iface_num = 2,
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.mem_size = (16 << 20),
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.flash0_size = 4*1024*1024,
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},
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{
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@ -179,6 +185,7 @@ static struct adm5120_board __initdata adm5120_boards[] = {
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.mach_type = MACH_ADM5120_BR6104K,
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.has_usb = 0,
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.iface_num = 5,
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.mem_size = (16 << 20),
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.flash0_size = 2*1024*1024,
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},
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{
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@ -926,19 +933,76 @@ static void __init adm5120_detect_cpuinfo(void)
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adm5120_speed += 50000000;
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}
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#if 1
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# define mem_dbg(f, ...) prom_printf("mem_detect: " f, ## __VA_ARGS__)
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static void adm5120_ndelay(u32 ns)
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{
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u32 t;
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SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
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SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
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t = (ns+640) / 640;
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t &= TIMER_PERIOD_MASK;
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SWITCH_WRITE(SWITCH_REG_TIMER, t | TIMER_TE);
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/* wait until the timer expires */
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do {
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t = SWITCH_READ(SWITCH_REG_TIMER_INT);
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} while ((t & TIMER_INT_TOS) == 0);
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/* leave the timer disabled */
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SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
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SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
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}
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#define MPMC_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
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#define MPMC_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
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extern void prom_printf(char *, ...);
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#if 1
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# define mem_dbg(f, a...) prom_printf("mem_detect: " f, ## a)
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#else
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# define mem_dbg(f, ...)
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# define mem_dbg(f, a...)
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#endif
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#define MEM_WR_DELAY 10000 /* 0.01 usec */
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static int mem_check_pattern(u8 *addr, unsigned long offs)
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{
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volatile u32 *p1 = (volatile u32 *)addr;
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volatile u32 *p2 = (volatile u32 *)(addr+offs);
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u32 t,u,v;
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/* save original value */
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t = *p1;
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u = *p2;
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if (t != u)
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return 0;
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v = 0x55555555;
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if (u == v)
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v = 0xAAAAAAAA;
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mem_dbg("write 0x%08lX to 0x%08lX\n", v, (unsigned long)p1);
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*p1 = v;
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mem_dbg("delay %d ns\n", MEM_WR_DELAY);
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adm5120_ndelay(MEM_WR_DELAY);
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u = *p2;
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mem_dbg("pattern at 0x%08lX is 0x%08lX\n", (unsigned long)p2, u);
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/* restore original value */
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*p1 = t;
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return (v == u);
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}
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static void __init adm5120_detect_memsize(void)
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{
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u32 memctrl;
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u32 size, maxsize;
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volatile u8 *p,*r;
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u8 t;
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u8 *p;
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memctrl = SWITCH_READ(SWITCH_REG_MEMCTRL);
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switch (memctrl & MEMCTRL_SDRS_MASK) {
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@ -956,71 +1020,45 @@ static void __init adm5120_detect_memsize(void)
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break;
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}
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/* FIXME: need to disable buffers for both SDRAM banks? */
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/* disable buffers for both SDRAM banks */
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mem_dbg("disable buffers for both banks\n");
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MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) & ~DC_BE);
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MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) & ~DC_BE);
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mem_dbg("checking for %ldMB chip\n",maxsize >> 20);
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mem_dbg("checking for %ldMB chip in 1st bank\n", maxsize >> 20);
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/* detect size of the 1st SDRAM bank */
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p = (volatile u8 *)KSEG1ADDR(0);
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t = *p;
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p = (u8 *)KSEG1ADDR(0);
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for (size = 2<<20; size <= (maxsize >> 1); size <<= 1) {
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#if 1
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r = (p+size);
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*p = 0x55;
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mem_dbg("1st pattern at 0x%lx is 0x%02x\n", size, *r);
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if (*r == 0x55) {
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*p = 0xAA;
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mem_dbg("2nd pattern at 0x%lx is 0x%02x\n", size, *r);
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if (*r == 0xAA) {
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/* mirrored address */
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mem_dbg("mirrored data found at 0x%lx\n", size);
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break;
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}
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if (mem_check_pattern(p, size)) {
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/* mirrored address */
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mem_dbg("mirrored data found at offset 0x%lX\n", size);
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break;
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}
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#else
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p[0] = 0x55;
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mem_dbg("1st pattern at 0x%lx is 0x%02x\n", size, p[size]);
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if (p[size] != 0x55)
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continue;
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p[0] = 0xAA;
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mem_dbg("2nd pattern at 0x%lx is 0x%02x\n", size, p[size]);
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if (p[size] != 0xAA)
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continue;
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/* mirrored address */
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mem_dbg("mirrored data found at 0x%lx\n", size);
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break;
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#endif
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}
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*p = t;
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mem_dbg("%ldMB chip found\n", size >> 20);
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mem_dbg("chip size in 1st bank is %ldMB\n", size >> 20);
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adm5120_memsize = size;
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if (size == (32 << 20))
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/* if bank size is 32MB, 2nd bank is not supported */
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if (size != maxsize)
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/* 2nd bank is not supported */
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goto out;
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if ((memctrl & MEMCTRL_SDR1_ENABLE) == 0)
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/* if 2nd bank is not enabled, we are done */
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/* 2nd bank is disabled */
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goto out;
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/*
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* some bootloaders enable 2nd bank, even if the 2nd SDRAM chip
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* are missing.
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*/
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mem_dbg("checking second bank\n");
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p += (maxsize+size)-1;
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t = *p;
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*p = 0x55;
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if (*p != 0x55)
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goto out;
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mem_dbg("check presence of 2nd bank\n");
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*p = 0xAA;
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if (*p != 0xAA)
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goto out;
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p = (u8 *)KSEG1ADDR(maxsize+size-4);
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if (mem_check_pattern(p, 0)) {
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adm5120_memsize += size;
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}
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*p = t;
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if (maxsize != size) {
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/* adjusting MECTRL register */
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memctrl &= ~(MEMCTRL_SDRS_MASK);
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@ -1040,11 +1078,21 @@ static void __init adm5120_detect_memsize(void)
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}
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SWITCH_WRITE(SWITCH_REG_MEMCTRL, memctrl);
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}
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size <<= 1;
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out:
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adm5120_memsize = size;
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mem_dbg("%ldMB memory found\n",size>>20);
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/* reenable buffer for both SDRAM banks */
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mem_dbg("enable buffers for both banks\n");
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MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) | DC_BE);
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MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) | DC_BE);
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mem_dbg("%dx%ldMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
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size >>20);
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size = adm5120_board_memsize();
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if (size > 0 && size != adm5120_memsize) {
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mem_dbg("wrong memory size detected, board settings will be used\n");
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adm5120_memsize = size;
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}
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}
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void __init adm5120_info_show(void)
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@ -1063,10 +1111,9 @@ void __init adm5120_info_show(void)
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void __init adm5120_info_init(void)
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{
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adm5120_detect_cpuinfo();
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adm5120_detect_memsize();
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adm5120_detect_board();
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adm5120_detect_memsize();
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adm5120_info_show();
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}
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@ -22,6 +22,7 @@ struct adm5120_board {
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unsigned long mach_type;
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unsigned int iface_num; /* Number of Ethernet interfaces */
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unsigned int has_usb; /* USB controller presence flag */
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u32 mem_size; /* onboard memory size */
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u32 flash0_size; /* Flash 0 size */
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};
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@ -79,4 +80,9 @@ static inline char *adm5120_board_name(void)
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return adm5120_board.name;
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}
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static inline u32 adm5120_board_memsize(void)
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{
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return adm5120_board.mem_size;
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}
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#endif /* _ADM5120_INFO_H */
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@ -0,0 +1,87 @@
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/*
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* $Id$
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*
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* ADM5120 MPMC (Multiport Memory Controller) register definitions
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*
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* Copyright (C) 2007 OpenWrt.org
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* Copyright (C) 2007 Gabor Juhos <juhosg@freemail.hu>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#ifndef _ADM5120_MPMC_H_
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#define _ADM5120_MPMC_H_
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#define MPMC_REG_CTRL 0x0000
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#define MPMC_REG_STATUS 0x0004
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#define MPMC_REG_CONF 0x0008
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#define MPMC_REG_DC 0x0020
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#define MPMC_REG_DR 0x0024
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#define MPMC_REG_DRP 0x0030
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#define MPMC_REG_DC0 0x0100
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#define MPMC_REG_DRC0 0x0104
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#define MPMC_REG_DC1 0x0120
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#define MPMC_REG_DRC1 0x0124
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#define MPMC_REG_DC2 0x0140
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#define MPMC_REG_DRC2 0x0144
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#define MPMC_REG_DC3 0x0160
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#define MPMC_REG_DRC3 0x0164
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#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */
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#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */
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#define MPMC_REG_SC2 0x0240
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#define MPMC_REG_SC3 0x0260
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#define MPMC_CTRL_AM ( 1 << 1 )
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/* Dynamic Control register bits */
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#define MPMC_DC_CE ( 1 << 0 )
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#define MPMC_DC_DMC ( 1 << 1 )
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#define MPMC_DC_SRR ( 1 << 2 )
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#define MPMC_DC_SI_SHIFT 7
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#define MPMC_DC_SI_MASK ( 3 << 7 )
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#define MPMC_DC_SI_NORMAL ( 0 << 7 )
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#define MPMC_DC_SI_MODE ( 1 << 7 )
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#define MPMC_DC_SI_PALL ( 2 << 7 )
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#define MPMC_DC_SI_NOP ( 3 << 7 )
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#define SRAM_REG_CONF 0x00
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#define SRAM_REG_WWE 0x04
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#define SRAM_REG_WOE 0x08
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#define SRAM_REG_WRD 0x0C
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#define SRAM_REG_WPG 0x10
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#define SRAM_REG_WWR 0x14
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#define SRAM_REG_WTR 0x18
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/* Dynamic Configuration register bits */
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#define DC_BE (1 << 19) /* buffer enable */
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#define DC_RW_SHIFT 28 /* shift for number of rows */
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#define DC_RW_MASK 0x03
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#define DC_NB_SHIFT 26 /* shift for number of banks */
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#define DC_NB_MASK 0x01
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#define DC_CW_SHIFT 22 /* shift for number of columns */
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#define DC_CW_MASK 0x07
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#define DC_DW_SHIFT 7 /* shift for device width */
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#define DC_DW_MASK 0x03
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/* Static Configuration register bits */
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#define SC_MW_MASK 0x03 /* memory width mask */
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#define SC_MW_8 0x00 /* 8 bit memory width */
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#define SC_MW_16 0x01 /* 16 bit memory width */
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#define SC_MW_32 0x02 /* 32 bit memory width */
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#endif /* _ADM5120_MPMC_H_ */
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@ -93,10 +93,15 @@
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#define MEMCTRL_SDRS_64M 0x04
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#define MEMCTRL_SDRS_128M 0x05
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#define MEMCTRL_SDR1_ENABLE ONEBIT(5) /* enable SDRAM bank 1 */
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#define MEMCTRL_SR0S_MASK BITMASK(3) /* SRAM0 size */
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#define MEMCTRL_SR0S_SHIFT 8
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#define MEMCTRL_SR1S_MASK BITMAKS(3) /* SRAM1 size */
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#define MEMCTRL_SR1S_SHIFT 16
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#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
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#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
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#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */
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#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */
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#define MEMCTRL_SRS_512K 0x01 /* 512KB*/
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#define MEMCTRL_SRS_1M 0x02 /* 1MB */
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#define MEMCTRL_SRS_2M 0x03 /* 2MB */
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#define MEMCTRL_SRS_4M 0x04 /* 4MB */
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/* GPIO_CONF0 register bits */
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#define GPIO_CONF0_MASK BITMASK(8)
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@ -109,6 +114,15 @@
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#define GPIO_CONF0_OE_MASK (0xFF << GPIO_CONF0_OE_SHIFT)
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#define GPIO_CONF0_OV_MASK (0xFF << GPIO_CONF0_OV_SHIFT)
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/* TIMER_INT register bits */
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#define TIMER_INT_TOS ONEBIT(1) /* time-out status */
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#define TIMER_INT_TOM ONEBIT(16) /* mask time-out interrupt */
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/* TIMER register bits */
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#define TIMER_PERIOD_MASK BITMASK(16) /* mask for timer period */
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#define TIMER_PERIOD_DEFAULT 0xFFFF /* default timer period */
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#define TIMER_TE ONEBIT(16) /* timer enable bit */
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/* PORTx_LED register bits */
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#define LED_MODE_MASK BITMASK(4)
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#define LED_MODE_INPUT 0
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@ -1,7 +1,7 @@
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CONFIG_32BIT=y
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# CONFIG_64BIT is not set
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# CONFIG_64BIT_PHYS_ADDR is not set
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CONFIG_ADM5120_HARDWARE_SWAB=y
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# CONFIG_ADM5120_HARDWARE_SWAB is not set
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CONFIG_ADM5120_NR_UARTS=2
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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