Add support for Atheros SoC (used in Fonera, Meraki) - Merry Christmas, everybody :)
SVN-Revision: 5898
This commit is contained in:
Felix Fietkau
parent
c4b3b0d9db
commit
216e8fcc55
25
target/linux/atheros-2.6/Makefile
Normal file
25
target/linux/atheros-2.6/Makefile
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@ -0,0 +1,25 @@
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#
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# Copyright (C) 2006 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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ARCH:=mips
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BOARD:=atheros
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BOARDNAME:=Atheros
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FEATURES:=jffs2
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define Target/Description
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Build firmware images for Atheros SoC boards (currently AR2315-AR2317)
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endef
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LINUX_VERSION:=2.6.19
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LINUX_RELEASE:=1
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LINUX_KERNEL_MD5SUM:=443c265b57e87eadc0c677c3acc37e20
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include $(INCLUDE_DIR)/kernel-build.mk
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DEFAULT_PACKAGES += kmod-madwifi
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$(eval $(call BuildKernel))
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1371
target/linux/atheros-2.6/config
Normal file
1371
target/linux/atheros-2.6/config
Normal file
File diff suppressed because it is too large
Load Diff
193
target/linux/atheros-2.6/config-diff
Normal file
193
target/linux/atheros-2.6/config-diff
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@ -0,0 +1,193 @@
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CONFIG_32BIT=y
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# CONFIG_64BIT is not set
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# CONFIG_64BIT_PHYS_ADDR is not set
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CONFIG_AP51=y
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CONFIG_AR2313=y
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CONFIG_AR5315=y
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CONFIG_AR531X=y
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CONFIG_AR531X_COBRA=y
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# CONFIG_ATM is not set
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CONFIG_BASE_SMALL=0
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# CONFIG_BT is not set
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_HAS_LLSC=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_SYNC=y
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# CONFIG_CPU_LITTLE_ENDIAN is not set
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CONFIG_CPU_MIPS32=y
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CONFIG_CPU_MIPS32_R1=y
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# CONFIG_CPU_MIPS32_R2 is not set
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# CONFIG_CPU_MIPS64_R1 is not set
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# CONFIG_CPU_MIPS64_R2 is not set
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CONFIG_CPU_MIPSR1=y
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# CONFIG_CPU_NEVADA is not set
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# CONFIG_CPU_R10000 is not set
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# CONFIG_CPU_R3000 is not set
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# CONFIG_CPU_R4300 is not set
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# CONFIG_CPU_R4X00 is not set
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# CONFIG_CPU_R5000 is not set
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# CONFIG_CPU_R5432 is not set
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# CONFIG_CPU_R6000 is not set
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# CONFIG_CPU_R8000 is not set
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# CONFIG_CPU_RM7000 is not set
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# CONFIG_CPU_RM9000 is not set
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# CONFIG_CPU_SB1 is not set
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CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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# CONFIG_CPU_TX39XX is not set
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# CONFIG_CPU_TX49XX is not set
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# CONFIG_CPU_VR41XX is not set
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# CONFIG_DDB5477 is not set
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# CONFIG_DM9000 is not set
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CONFIG_DMA_NEED_PCI_MAP_STATE=y
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CONFIG_DMA_NONCOHERENT=y
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# CONFIG_FIRMWARE_EDID is not set
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CONFIG_FS_POSIX_ACL=y
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# CONFIG_FUSE_FS is not set
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CONFIG_GENERIC_FIND_NEXT_BIT=y
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# CONFIG_GEN_RTC is not set
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CONFIG_HAVE_STD_PC_SERIAL_PORT=y
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# CONFIG_HOSTAP is not set
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CONFIG_HW_RANDOM=y
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CONFIG_HZ=100
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CONFIG_HZ_100=y
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# CONFIG_HZ_1024 is not set
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# CONFIG_HZ_128 is not set
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# CONFIG_HZ_250 is not set
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# CONFIG_HZ_256 is not set
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# CONFIG_HZ_48 is not set
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# CONFIG_I2C is not set
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# CONFIG_IDE is not set
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# CONFIG_IEEE80211 is not set
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQ_CPU=y
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CONFIG_JFFS2_FS_DEBUG=0
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# CONFIG_MACH_DECSTATION is not set
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# CONFIG_MACH_JAZZ is not set
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# CONFIG_MACH_VR41XX is not set
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CONFIG_MINI_FO=m
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CONFIG_MIPS=y
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# CONFIG_MIPS_ATLAS is not set
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# CONFIG_MIPS_BOSPORUS is not set
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# CONFIG_MIPS_COBALT is not set
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# CONFIG_MIPS_DB1000 is not set
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# CONFIG_MIPS_DB1100 is not set
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# CONFIG_MIPS_DB1200 is not set
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# CONFIG_MIPS_DB1500 is not set
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# CONFIG_MIPS_DB1550 is not set
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# CONFIG_MIPS_EV64120 is not set
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CONFIG_MIPS_L1_CACHE_SHIFT=5
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# CONFIG_MIPS_MALTA is not set
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# CONFIG_MIPS_MIRAGE is not set
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# CONFIG_MIPS_MTX1 is not set
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CONFIG_MIPS_MT_DISABLED=y
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# CONFIG_MIPS_MT_SMP is not set
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# CONFIG_MIPS_MT_SMTC is not set
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# CONFIG_MIPS_PB1000 is not set
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# CONFIG_MIPS_PB1100 is not set
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# CONFIG_MIPS_PB1200 is not set
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# CONFIG_MIPS_PB1500 is not set
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# CONFIG_MIPS_PB1550 is not set
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# CONFIG_MIPS_SEAD is not set
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# CONFIG_MIPS_SIM is not set
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# CONFIG_MIPS_VPE_LOADER is not set
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# CONFIG_MIPS_XXS1500 is not set
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# CONFIG_MOMENCO_JAGUAR_ATX is not set
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# CONFIG_MOMENCO_OCELOT is not set
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# CONFIG_MOMENCO_OCELOT_3 is not set
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# CONFIG_MOMENCO_OCELOT_C is not set
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# CONFIG_MOMENCO_OCELOT_G is not set
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CONFIG_MTD=y
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# CONFIG_MTD_ABSENT is not set
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CONFIG_MTD_BLOCK=y
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# CONFIG_MTD_BLOCK2MTD is not set
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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CONFIG_MTD_CFI_AMDSTD=y
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# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
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# CONFIG_MTD_CFI_GEOMETRY is not set
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CONFIG_MTD_CFI_I1=y
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CONFIG_MTD_CFI_I2=y
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# CONFIG_MTD_CFI_I4 is not set
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# CONFIG_MTD_CFI_I8 is not set
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# CONFIG_MTD_CFI_INTELEXT is not set
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# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
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CONFIG_MTD_CFI_NOSWAP=y
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# CONFIG_MTD_CFI_STAA is not set
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CONFIG_MTD_CFI_UTIL=y
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CONFIG_MTD_CHAR=y
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# CONFIG_MTD_CMDLINE_PARTS is not set
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CONFIG_MTD_COMPLEX_MAPPINGS=y
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# CONFIG_MTD_CONCAT is not set
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# CONFIG_MTD_DEBUG is not set
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# CONFIG_MTD_DOC2000 is not set
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# CONFIG_MTD_DOC2001 is not set
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# CONFIG_MTD_DOC2001PLUS is not set
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CONFIG_MTD_GEN_PROBE=y
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# CONFIG_MTD_JEDECPROBE is not set
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CONFIG_MTD_MAP_BANK_WIDTH_1=y
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# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
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CONFIG_MTD_MAP_BANK_WIDTH_2=y
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# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
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CONFIG_MTD_MAP_BANK_WIDTH_4=y
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# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
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# CONFIG_MTD_MTDRAM is not set
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# CONFIG_MTD_NAND is not set
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# CONFIG_MTD_OBSOLETE_CHIPS is not set
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# CONFIG_MTD_ONENAND is not set
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# CONFIG_MTD_OTP is not set
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CONFIG_MTD_PARTITIONS=y
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# CONFIG_MTD_PHRAM is not set
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# CONFIG_MTD_PHYSMAP is not set
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# CONFIG_MTD_PHYSMAP_BANKWIDTH is not set
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# CONFIG_MTD_PHYSMAP_LEN is not set
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# CONFIG_MTD_PHYSMAP_START is not set
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# CONFIG_MTD_PLATRAM is not set
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# CONFIG_MTD_RAM is not set
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CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
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CONFIG_MTD_REDBOOT_PARTS=y
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CONFIG_MTD_REDBOOT_PARTS_READONLY=y
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# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
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# CONFIG_MTD_ROM is not set
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# CONFIG_MTD_SLRAM is not set
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CONFIG_MTD_SPIFLASH=y
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# CONFIG_PAGE_SIZE_16KB is not set
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CONFIG_PAGE_SIZE_4KB=y
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# CONFIG_PAGE_SIZE_64KB is not set
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# CONFIG_PAGE_SIZE_8KB is not set
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# CONFIG_PCCARD is not set
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# CONFIG_PMC_YOSEMITE is not set
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# CONFIG_PNX8550_JBS is not set
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# CONFIG_PNX8550_V2PCI is not set
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# CONFIG_RTC is not set
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CONFIG_RWSEM_GENERIC_SPINLOCK=y
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CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
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# CONFIG_SERIAL_8250_EXTENDED is not set
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CONFIG_SERIAL_8250_NR_UARTS=1
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CONFIG_SERIAL_8250_RUNTIME_UARTS=1
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# CONFIG_SGI_IP22 is not set
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# CONFIG_SGI_IP27 is not set
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# CONFIG_SGI_IP32 is not set
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# CONFIG_SIBYTE_BIGSUR is not set
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# CONFIG_SIBYTE_CARMEL is not set
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# CONFIG_SIBYTE_CRHINE is not set
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# CONFIG_SIBYTE_CRHONE is not set
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# CONFIG_SIBYTE_LITTLESUR is not set
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# CONFIG_SIBYTE_PTSWARM is not set
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# CONFIG_SIBYTE_RHONE is not set
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# CONFIG_SIBYTE_SENTOSA is not set
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# CONFIG_SIBYTE_SWARM is not set
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# CONFIG_SOFT_WATCHDOG is not set
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# CONFIG_SPARSEMEM_STATIC is not set
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CONFIG_SYS_HAS_CPU_MIPS32_R1=y
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CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
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# CONFIG_TOSHIBA_JMR3927 is not set
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# CONFIG_TOSHIBA_RBTX4927 is not set
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# CONFIG_TOSHIBA_RBTX4938 is not set
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CONFIG_TRAD_SIGNALS=y
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# CONFIG_UNUSED_SYMBOLS is not set
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# CONFIG_USB_ARCH_HAS_EHCI is not set
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# CONFIG_USB_ARCH_HAS_HCD is not set
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# CONFIG_USB_ARCH_HAS_OHCI is not set
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23
target/linux/atheros-2.6/image/Makefile
Normal file
23
target/linux/atheros-2.6/image/Makefile
Normal file
@ -0,0 +1,23 @@
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#
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# Copyright (C) 2006 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/image.mk
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define Image/BuildKernel
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cp $(KDIR)/linux-*/vmlinux $(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-vmlinux.elf
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gzip -9 -c $(KDIR)/vmlinux > $(KDIR)/vmlinux.bin.gz
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$(STAGING_DIR)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.bin.l7
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dd if=$(KDIR)/vmlinux.bin.l7 of=$(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-vmlinux.lzma bs=65536 conv=sync
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dd if=$(KDIR)/vmlinux.bin.gz of=$(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-vmlinux.gz bs=65536 conv=sync
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endef
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define Image/Build
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dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(KERNEL)-root.$(1) bs=128k conv=sync
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endef
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$(eval $(call BuildImage))
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1926
target/linux/atheros-2.6/patches/100-board.patch
Normal file
1926
target/linux/atheros-2.6/patches/100-board.patch
Normal file
File diff suppressed because it is too large
Load Diff
750
target/linux/atheros-2.6/patches/110-spiflash.patch
Normal file
750
target/linux/atheros-2.6/patches/110-spiflash.patch
Normal file
@ -0,0 +1,750 @@
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diff -urN linux.old/drivers/mtd/devices/Kconfig linux.dev/drivers/mtd/devices/Kconfig
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--- linux.old/drivers/mtd/devices/Kconfig 2006-11-29 22:57:37.000000000 +0100
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+++ linux.dev/drivers/mtd/devices/Kconfig 2006-12-15 00:03:11.000000000 +0100
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@@ -68,6 +68,10 @@
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used for program and data storage. Set up your spi devices
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with the right board-specific platform data.
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+config MTD_SPIFLASH
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+ tristate "Atheros AR2315/6/7 SPI Flash support"
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+ depends on MTD && AR531X_COBRA
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+
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config MTD_SLRAM
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tristate "Uncached system RAM"
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depends on MTD
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diff -urN linux.old/drivers/mtd/devices/Makefile linux.dev/drivers/mtd/devices/Makefile
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--- linux.old/drivers/mtd/devices/Makefile 2006-11-29 22:57:37.000000000 +0100
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+++ linux.dev/drivers/mtd/devices/Makefile 2006-12-15 00:03:11.000000000 +0100
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@@ -17,3 +17,4 @@
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obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
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obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
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obj-$(CONFIG_MTD_M25P80) += m25p80.o
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+obj-$(CONFIG_MTD_SPIFLASH) += spiflash.o
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diff -urN linux.old/drivers/mtd/devices/spiflash.c linux.dev/drivers/mtd/devices/spiflash.c
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--- linux.old/drivers/mtd/devices/spiflash.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux.dev/drivers/mtd/devices/spiflash.c 2006-12-15 08:26:11.000000000 +0100
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@@ -0,0 +1,595 @@
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+
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+/*
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+ * MTD driver for the SPI Flash Memory support.
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+ *
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+ * Copyright (c) 2005-2006 Atheros Communications Inc.
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+ * Copyright (C) 2006 FON Technology, SL.
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+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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+ *
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+ * This code is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+/*===========================================================================
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+** !!!! VERY IMPORTANT NOTICE !!!! FLASH DATA STORED IN LITTLE ENDIAN FORMAT
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+**
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+** This module contains the Serial Flash access routines for the Atheros SOC.
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+** The Atheros SOC integrates a SPI flash controller that is used to access
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+** serial flash parts. The SPI flash controller executes in "Little Endian"
|
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+** mode. THEREFORE, all WRITES and READS from the MIPS CPU must be
|
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+** BYTESWAPPED! The SPI Flash controller hardware by default performs READ
|
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+** ONLY byteswapping when accessed via the SPI Flash Alias memory region
|
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+** (Physical Address 0x0800_0000 - 0x0fff_ffff). The data stored in the
|
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+** flash sectors is stored in "Little Endian" format.
|
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+**
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+** The spiflash_write() routine performs byteswapping on all write
|
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+** operations.
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+**===========================================================================*/
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/types.h>
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+#include <linux/version.h>
|
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+#include <linux/errno.h>
|
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+#include <linux/slab.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/squashfs_fs.h>
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+#include <linux/root_dev.h>
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+#include <asm/delay.h>
|
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+#include <asm/io.h>
|
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+#include "spiflash.h"
|
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+
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+/* debugging */
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+/* #define SPIFLASH_DEBUG */
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+
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+#ifndef __BIG_ENDIAN
|
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+#error This driver currently only works with big endian CPU.
|
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+#endif
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+
|
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+#define MAX_PARTS 32
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+
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+static char module_name[] = "spiflash";
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+
|
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+#define MIN(a,b) ((a) < (b) ? (a) : (b))
|
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+#define FALSE 0
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+#define TRUE 1
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+
|
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+#define ROOTFS_NAME "rootfs"
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+
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+static __u32 spiflash_regread32(int reg);
|
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+static void spiflash_regwrite32(int reg, __u32 data);
|
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+static __u32 spiflash_sendcmd (int op);
|
||||
+
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+static void __init spidata_init(void);
|
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+int __init spiflash_init (void);
|
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+void __exit spiflash_exit (void);
|
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+static int spiflash_probe (void);
|
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+static int spiflash_erase (struct mtd_info *mtd,struct erase_info *instr);
|
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+static int spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf);
|
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+static int spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf);
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+
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+/* Flash configuration table */
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+struct flashconfig {
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+ __u32 byte_cnt;
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+ __u32 sector_cnt;
|
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+ __u32 sector_size;
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+ __u32 cs_addrmask;
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+} flashconfig_tbl[MAX_FLASH] =
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+ {
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+ { 0, 0, 0, 0},
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+ { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT, STM_1MB_SECTOR_SIZE, 0x0},
|
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+ { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT, STM_2MB_SECTOR_SIZE, 0x0},
|
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+ { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT, STM_4MB_SECTOR_SIZE, 0x0},
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+ { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT, STM_8MB_SECTOR_SIZE, 0x0}
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||||
+ };
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||||
+
|
||||
+/* Mapping of generic opcodes to STM serial flash opcodes */
|
||||
+struct opcodes {
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+ __u16 code;
|
||||
+ __s8 tx_cnt;
|
||||
+ __s8 rx_cnt;
|
||||
+} stm_opcodes[] = {
|
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+ {STM_OP_WR_ENABLE, 1, 0},
|
||||
+ {STM_OP_WR_DISABLE, 1, 0},
|
||||
+ {STM_OP_RD_STATUS, 1, 1},
|
||||
+ {STM_OP_WR_STATUS, 1, 0},
|
||||
+ {STM_OP_RD_DATA, 4, 4},
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||||
+ {STM_OP_FAST_RD_DATA, 1, 0},
|
||||
+ {STM_OP_PAGE_PGRM, 8, 0},
|
||||
+ {STM_OP_SECTOR_ERASE, 4, 0},
|
||||
+ {STM_OP_BULK_ERASE, 1, 0},
|
||||
+ {STM_OP_DEEP_PWRDOWN, 1, 0},
|
||||
+ {STM_OP_RD_SIG, 4, 1}
|
||||
+};
|
||||
+
|
||||
+/* Driver private data structure */
|
||||
+struct spiflash_data {
|
||||
+ struct mtd_info *mtd;
|
||||
+ struct mtd_partition *parsed_parts; /* parsed partitions */
|
||||
+ void *spiflash_readaddr; /* memory mapped data for read */
|
||||
+ void *spiflash_mmraddr; /* memory mapped register space */
|
||||
+ spinlock_t mutex;
|
||||
+};
|
||||
+
|
||||
+static struct spiflash_data *spidata;
|
||||
+
|
||||
+extern int parse_redboot_partitions(struct mtd_info *master, struct mtd_partition **pparts);
|
||||
+
|
||||
+/***************************************************************************************************/
|
||||
+
|
||||
+static __u32
|
||||
+spiflash_regread32(int reg)
|
||||
+{
|
||||
+ volatile __u32 *data = (__u32 *)(spidata->spiflash_mmraddr + reg);
|
||||
+
|
||||
+ return (*data);
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+spiflash_regwrite32(int reg, __u32 data)
|
||||
+{
|
||||
+ volatile __u32 *addr = (__u32 *)(spidata->spiflash_mmraddr + reg);
|
||||
+
|
||||
+ *addr = data;
|
||||
+ return;
|
||||
+}
|
||||
+
|
||||
+static __u32
|
||||
+spiflash_sendcmd (int op)
|
||||
+{
|
||||
+ __u32 reg;
|
||||
+ __u32 mask;
|
||||
+ struct opcodes *ptr_opcode;
|
||||
+
|
||||
+ ptr_opcode = &stm_opcodes[op];
|
||||
+
|
||||
+ do {
|
||||
+ reg = spiflash_regread32(SPI_FLASH_CTL);
|
||||
+ } while (reg & SPI_CTL_BUSY);
|
||||
+
|
||||
+ spiflash_regwrite32(SPI_FLASH_OPCODE, ptr_opcode->code);
|
||||
+
|
||||
+ reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt |
|
||||
+ (ptr_opcode->rx_cnt << 4) | SPI_CTL_START;
|
||||
+
|
||||
+ spiflash_regwrite32(SPI_FLASH_CTL, reg);
|
||||
+
|
||||
+ if (ptr_opcode->rx_cnt > 0) {
|
||||
+ do {
|
||||
+ reg = spiflash_regread32(SPI_FLASH_CTL);
|
||||
+ } while (reg & SPI_CTL_BUSY);
|
||||
+
|
||||
+ reg = (__u32) spiflash_regread32(SPI_FLASH_DATA);
|
||||
+
|
||||
+ switch (ptr_opcode->rx_cnt) {
|
||||
+ case 1:
|
||||
+ mask = 0x000000ff;
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ mask = 0x0000ffff;
|
||||
+ break;
|
||||
+ case 3:
|
||||
+ mask = 0x00ffffff;
|
||||
+ break;
|
||||
+ default:
|
||||
+ mask = 0xffffffff;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ reg &= mask;
|
||||
+ }
|
||||
+ else {
|
||||
+ reg = 0;
|
||||
+ }
|
||||
+
|
||||
+ return reg;
|
||||
+}
|
||||
+
|
||||
+/* Probe SPI flash device
|
||||
+ * Function returns 0 for failure.
|
||||
+ * and flashconfig_tbl array index for success.
|
||||
+ */
|
||||
+static int
|
||||
+spiflash_probe (void)
|
||||
+{
|
||||
+ __u32 sig;
|
||||
+ int flash_size;
|
||||
+
|
||||
+ if (!spidata)
|
||||
+ spidata_init();
|
||||
+
|
||||
+ if (!spidata) /* init failed */
|
||||
+ return 0;
|
||||
+
|
||||
+ /* Read the signature on the flash device */
|
||||
+ sig = spiflash_sendcmd(SPI_RD_SIG);
|
||||
+
|
||||
+ switch (sig) {
|
||||
+ case STM_8MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_1MB;
|
||||
+ break;
|
||||
+ case STM_16MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_2MB;
|
||||
+ break;
|
||||
+ case STM_32MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_4MB;
|
||||
+ break;
|
||||
+ case STM_64MBIT_SIGNATURE:
|
||||
+ flash_size = FLASH_8MB;
|
||||
+ break;
|
||||
+ default:
|
||||
+ printk (KERN_WARNING "%s: Read of flash device signature failed!\n", module_name);
|
||||
+ return (0);
|
||||
+ }
|
||||
+
|
||||
+ return (flash_size);
|
||||
+}
|
||||
+
|
||||
+
|
||||
+static int
|
||||
+spiflash_erase (struct mtd_info *mtd,struct erase_info *instr)
|
||||
+{
|
||||
+ struct opcodes *ptr_opcode;
|
||||
+ __u32 temp, reg;
|
||||
+ int finished = FALSE;
|
||||
+
|
||||
+#ifdef SPIFLASH_DEBUG
|
||||
+ printk (KERN_DEBUG "%s(addr = 0x%.8x, len = %d)\n",__FUNCTION__,instr->addr,instr->len);
|
||||
+#endif
|
||||
+
|
||||
+ /* sanity checks */
|
||||
+ if (instr->addr + instr->len > mtd->size) return (-EINVAL);
|
||||
+
|
||||
+ ptr_opcode = &stm_opcodes[SPI_SECTOR_ERASE];
|
||||
+
|
||||
+ temp = ((__u32)instr->addr << 8) | (__u32)(ptr_opcode->code);
|
||||
+ spin_lock(&spidata->mutex);
|
||||
+ spiflash_sendcmd(SPI_WRITE_ENABLE);
|
||||
+ do {
|
||||
+ schedule();
|
||||
+ reg = spiflash_regread32(SPI_FLASH_CTL);
|
||||
+ } while (reg & SPI_CTL_BUSY);
|
||||
+
|
||||
+ spiflash_regwrite32(SPI_FLASH_OPCODE, temp);
|
||||
+
|
||||
+ reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | ptr_opcode->tx_cnt | SPI_CTL_START;
|
||||
+ spiflash_regwrite32(SPI_FLASH_CTL, reg);
|
||||
+
|
||||
+ do {
|
||||
+ schedule();
|
||||
+ reg = spiflash_sendcmd(SPI_RD_STATUS);
|
||||
+ if (!(reg & SPI_STATUS_WIP)) {
|
||||
+ finished = TRUE;
|
||||
+ }
|
||||
+ } while (!finished);
|
||||
+ spin_unlock(&spidata->mutex);
|
||||
+
|
||||
+ instr->state = MTD_ERASE_DONE;
|
||||
+ if (instr->callback) instr->callback (instr);
|
||||
+
|
||||
+#ifdef SPIFLASH_DEBUG
|
||||
+ printk (KERN_DEBUG "%s return\n",__FUNCTION__);
|
||||
+#endif
|
||||
+ return (0);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+spiflash_read (struct mtd_info *mtd, loff_t from,size_t len,size_t *retlen,u_char *buf)
|
||||
+{
|
||||
+ u_char *read_addr;
|
||||
+
|
||||
+#ifdef SPIFLASH_DEBUG
|
||||
+ printk (KERN_DEBUG "%s(from = 0x%.8x, len = %d)\n",__FUNCTION__,(__u32) from,(int)len);
|
||||
+#endif
|
||||
+
|
||||
+ /* sanity checks */
|
||||
+ if (!len) return (0);
|
||||
+ if (from + len > mtd->size) return (-EINVAL);
|
||||
+
|
||||
+
|
||||
+ /* we always read len bytes */
|
||||
+ *retlen = len;
|
||||
+
|
||||
+ read_addr = (u_char *)(spidata->spiflash_readaddr + from);
|
||||
+ spin_lock(&spidata->mutex);
|
||||
+ memcpy(buf, read_addr, len);
|
||||
+ spin_unlock(&spidata->mutex);
|
||||
+
|
||||
+ return (0);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+spiflash_write (struct mtd_info *mtd,loff_t to,size_t len,size_t *retlen,const u_char *buf)
|
||||
+{
|
||||
+ int done = FALSE, page_offset, bytes_left, finished;
|
||||
+ __u32 xact_len, spi_data = 0, opcode, reg;
|
||||
+
|
||||
+#ifdef SPIFLASH_DEBUG
|
||||
+ printk (KERN_DEBUG "%s(to = 0x%.8x, len = %d)\n",__FUNCTION__,(__u32) to,len);
|
||||
+#endif
|
||||
+
|
||||
+ *retlen = 0;
|
||||
+
|
||||
+ /* sanity checks */
|
||||
+ if (!len) return (0);
|
||||
+ if (to + len > mtd->size) return (-EINVAL);
|
||||
+
|
||||
+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code;
|
||||
+ bytes_left = len;
|
||||
+
|
||||
+ while (done == FALSE) {
|
||||
+ xact_len = MIN(bytes_left, sizeof(__u32));
|
||||
+
|
||||
+ /* 32-bit writes cannot span across a page boundary
|
||||
+ * (256 bytes). This types of writes require two page
|
||||
+ * program operations to handle it correctly. The STM part
|
||||
+ * will write the overflow data to the beginning of the
|
||||
+ * current page as opposed to the subsequent page.
|
||||
+ */
|
||||
+ page_offset = (to & (STM_PAGE_SIZE - 1)) + xact_len;
|
||||
+
|
||||
+ if (page_offset > STM_PAGE_SIZE) {
|
||||
+ xact_len -= (page_offset - STM_PAGE_SIZE);
|
||||
+ }
|
||||
+
|
||||
+ spin_lock(&spidata->mutex);
|
||||
+ spiflash_sendcmd(SPI_WRITE_ENABLE);
|
||||
+
|
||||
+ do {
|
||||
+ schedule();
|
||||
+ reg = spiflash_regread32(SPI_FLASH_CTL);
|
||||
+ } while (reg & SPI_CTL_BUSY);
|
||||
+
|
||||
+ switch (xact_len) {
|
||||
+ case 1:
|
||||
+ spi_data = (u32) ((u8) *buf);
|
||||
+ break;
|
||||
+ case 2:
|
||||
+ spi_data = (buf[1] << 8) | buf[0];
|
||||
+ break;
|
||||
+ case 3:
|
||||
+ spi_data = (buf[2] << 16) | (buf[1] << 8) | buf[0];
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ spi_data = (buf[3] << 24) | (buf[2] << 16) |
|
||||
+ (buf[1] << 8) | buf[0];
|
||||
+ break;
|
||||
+ default:
|
||||
+ printk("spiflash_write: default case\n");
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ spiflash_regwrite32(SPI_FLASH_DATA, spi_data);
|
||||
+ opcode = (opcode & SPI_OPCODE_MASK) | ((__u32)to << 8);
|
||||
+ spiflash_regwrite32(SPI_FLASH_OPCODE, opcode);
|
||||
+
|
||||
+ reg = (reg & ~SPI_CTL_TX_RX_CNT_MASK) | (xact_len + 4) | SPI_CTL_START;
|
||||
+ spiflash_regwrite32(SPI_FLASH_CTL, reg);
|
||||
+ finished = FALSE;
|
||||
+
|
||||
+ do {
|
||||
+ schedule();
|
||||
+ reg = spiflash_sendcmd(SPI_RD_STATUS);
|
||||
+ if (!(reg & SPI_STATUS_WIP)) {
|
||||
+ finished = TRUE;
|
||||
+ }
|
||||
+ } while (!finished);
|
||||
+ spin_unlock(&spidata->mutex);
|
||||
+
|
||||
+ bytes_left -= xact_len;
|
||||
+ to += xact_len;
|
||||
+ buf += xact_len;
|
||||
+
|
||||
+ *retlen += xact_len;
|
||||
+
|
||||
+ if (bytes_left == 0) {
|
||||
+ done = TRUE;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ return (0);
|
||||
+}
|
||||
+
|
||||
+static void __init spidata_init(void)
|
||||
+{
|
||||
+ if (spidata)
|
||||
+ return;
|
||||
+
|
||||
+ spidata = kmalloc(sizeof(struct spiflash_data), GFP_KERNEL);
|
||||
+ spin_lock_init(&spidata->mutex);
|
||||
+
|
||||
+ if (!spidata)
|
||||
+ return;
|
||||
+
|
||||
+ spidata->spiflash_mmraddr = ioremap_nocache(SPI_FLASH_MMR, SPI_FLASH_MMR_SIZE);
|
||||
+
|
||||
+ if (!spidata->spiflash_mmraddr) {
|
||||
+ printk (KERN_WARNING "%s: Failed to map flash device\n", module_name);
|
||||
+ kfree(spidata);
|
||||
+ spidata = NULL;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_MTD_PARTITIONS
|
||||
+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
|
||||
+#endif
|
||||
+
|
||||
+int __init
|
||||
+spiflash_init (void)
|
||||
+{
|
||||
+ int result = -1, i, j;
|
||||
+ u32 len;
|
||||
+ int index, num_parts;
|
||||
+ struct mtd_info *mtd;
|
||||
+ struct mtd_partition *mtd_parts;
|
||||
+ char *buf;
|
||||
+ struct mtd_partition *part;
|
||||
+ struct squashfs_super_block *sb;
|
||||
+ u32 config_start;
|
||||
+
|
||||
+ spidata_init();
|
||||
+
|
||||
+ if (!spidata)
|
||||
+ return (-ENXIO);
|
||||
+
|
||||
+ mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
|
||||
+ if (!mtd) {
|
||||
+ kfree(spidata);
|
||||
+ return (-ENXIO);
|
||||
+ }
|
||||
+
|
||||
+ printk ("MTD driver for SPI flash.\n");
|
||||
+ printk ("%s: Probing for Serial flash ...\n", module_name);
|
||||
+ if (!(index = spiflash_probe ())) {
|
||||
+ printk (KERN_WARNING "%s: Found no serial flash device\n", module_name);
|
||||
+ kfree(mtd);
|
||||
+ kfree(spidata);
|
||||
+ return (-ENXIO);
|
||||
+ }
|
||||
+
|
||||
+ printk ("%s: Found SPI serial Flash.\n", module_name);
|
||||
+
|
||||
+ spidata->spiflash_readaddr = ioremap_nocache(SPI_FLASH_READ, flashconfig_tbl[index].byte_cnt);
|
||||
+ if (!spidata->spiflash_readaddr) {
|
||||
+ printk (KERN_WARNING "%s: Failed to map flash device\n", module_name);
|
||||
+ kfree(mtd);
|
||||
+ kfree(spidata);
|
||||
+ return (-ENXIO);
|
||||
+ }
|
||||
+
|
||||
+ mtd->name = module_name;
|
||||
+ mtd->type = MTD_NORFLASH;
|
||||
+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
|
||||
+ mtd->size = flashconfig_tbl[index].byte_cnt;
|
||||
+ mtd->erasesize = flashconfig_tbl[index].sector_size;
|
||||
+ mtd->writesize = 1;
|
||||
+ mtd->numeraseregions = 0;
|
||||
+ mtd->eraseregions = NULL;
|
||||
+ mtd->erase = spiflash_erase;
|
||||
+ mtd->read = spiflash_read;
|
||||
+ mtd->write = spiflash_write;
|
||||
+ mtd->owner = THIS_MODULE;
|
||||
+
|
||||
+#ifdef SPIFLASH_DEBUG
|
||||
+ printk (KERN_DEBUG
|
||||
+ "mtd->name = %s\n"
|
||||
+ "mtd->size = 0x%.8x (%uM)\n"
|
||||
+ "mtd->erasesize = 0x%.8x (%uK)\n"
|
||||
+ "mtd->numeraseregions = %d\n",
|
||||
+ mtd->name,
|
||||
+ mtd->size, mtd->size / (1024*1024),
|
||||
+ mtd->erasesize, mtd->erasesize / 1024,
|
||||
+ mtd->numeraseregions);
|
||||
+
|
||||
+ if (mtd->numeraseregions) {
|
||||
+ for (result = 0; result < mtd->numeraseregions; result++) {
|
||||
+ printk (KERN_DEBUG
|
||||
+ "\n\n"
|
||||
+ "mtd->eraseregions[%d].offset = 0x%.8x\n"
|
||||
+ "mtd->eraseregions[%d].erasesize = 0x%.8x (%uK)\n"
|
||||
+ "mtd->eraseregions[%d].numblocks = %d\n",
|
||||
+ result,mtd->eraseregions[result].offset,
|
||||
+ result,mtd->eraseregions[result].erasesize,mtd->eraseregions[result].erasesize / 1024,
|
||||
+ result,mtd->eraseregions[result].numblocks);
|
||||
+ }
|
||||
+ }
|
||||
+#endif
|
||||
+
|
||||
+ /* parse redboot partitions */
|
||||
+ num_parts = parse_mtd_partitions(mtd, part_probe_types, &spidata->parsed_parts, 0);
|
||||
+
|
||||
+ mtd_parts = kzalloc(sizeof(struct mtd_partition) * MAX_PARTS, GFP_KERNEL);
|
||||
+ buf = kmalloc(mtd->erasesize, GFP_KERNEL);
|
||||
+ sb = (struct squashfs_super_block *) buf;
|
||||
+ for (i = j = 0; i < num_parts; i++, j++) {
|
||||
+ part = &mtd_parts[j];
|
||||
+ memcpy(part, &spidata->parsed_parts[i], sizeof(struct mtd_partition));
|
||||
+
|
||||
+ if (!strcmp(part->name, ROOTFS_NAME)) {
|
||||
+ /* create the root device */
|
||||
+ ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, i);
|
||||
+
|
||||
+ part->size -= mtd->erasesize;
|
||||
+ config_start = part->offset + part->size;
|
||||
+
|
||||
+ while ((mtd->read(mtd, part->offset, mtd->erasesize, &len, buf) == 0) &&
|
||||
+ (len == mtd->erasesize) &&
|
||||
+ (*((u32 *) buf) == SQUASHFS_MAGIC) &&
|
||||
+ (sb->bytes_used > 0)) {
|
||||
+
|
||||
+ /* this is squashfs, allocate another partition starting from the end of filesystem data */
|
||||
+ memcpy(&mtd_parts[j + 1], part, sizeof(struct mtd_partition));
|
||||
+
|
||||
+ len = (u32) sb->bytes_used;
|
||||
+ len += (part->offset & 0x000fffff);
|
||||
+ len += (mtd->erasesize - 1);
|
||||
+ len &= ~(mtd->erasesize - 1);
|
||||
+ len -= (part->offset & 0x000fffff);
|
||||
+
|
||||
+ if (len + mtd->erasesize > part->size)
|
||||
+ break;
|
||||
+
|
||||
+ part = &mtd_parts[++j];
|
||||
+
|
||||
+ part->offset += len;
|
||||
+ part->size -= len;
|
||||
+
|
||||
+ part->name = kmalloc(10, GFP_KERNEL);
|
||||
+ sprintf(part->name, "rootfs%d", j - i);
|
||||
+ }
|
||||
+ }
|
||||
+ if (!strcmp(part->name, "RedBoot config")) {
|
||||
+ /* add anoterh partition for the board config data */
|
||||
+ memcpy(&mtd_parts[j + 1], part, sizeof(struct mtd_partition));
|
||||
+ j++;
|
||||
+ part = &mtd_parts[j];
|
||||
+ part->offset += part->size;
|
||||
+ part->size = mtd->erasesize;
|
||||
+
|
||||
+ part->name = kmalloc(16, GFP_KERNEL);
|
||||
+ sprintf(part->name, "board_config");
|
||||
+ }
|
||||
+ }
|
||||
+ num_parts += j - i;
|
||||
+ kfree(buf);
|
||||
+
|
||||
+#ifdef SPIFLASH_DEBUG
|
||||
+ printk (KERN_DEBUG "Found %d redboot partitions\n", num_parts);
|
||||
+#endif
|
||||
+ if (num_parts) {
|
||||
+ result = add_mtd_partitions(mtd, mtd_parts, num_parts);
|
||||
+ } else {
|
||||
+#ifdef SPIFLASH_DEBUG
|
||||
+ printk (KERN_DEBUG "Did not find any redboot partitions\n");
|
||||
+#endif
|
||||
+ kfree(mtd);
|
||||
+ kfree(spidata);
|
||||
+ return (-ENXIO);
|
||||
+ }
|
||||
+
|
||||
+ spidata->mtd = mtd;
|
||||
+
|
||||
+ return (result);
|
||||
+}
|
||||
+
|
||||
+void __exit
|
||||
+spiflash_exit (void)
|
||||
+{
|
||||
+ if (spidata && spidata->parsed_parts) {
|
||||
+ del_mtd_partitions (spidata->mtd);
|
||||
+ kfree(spidata->mtd);
|
||||
+ kfree(spidata);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+module_init (spiflash_init);
|
||||
+module_exit (spiflash_exit);
|
||||
+
|
||||
+MODULE_LICENSE("GPL");
|
||||
+MODULE_AUTHOR("Atheros Communications Inc");
|
||||
+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros SOC");
|
||||
+
|
||||
diff -urN linux.old/drivers/mtd/devices/spiflash.h linux.dev/drivers/mtd/devices/spiflash.h
|
||||
--- linux.old/drivers/mtd/devices/spiflash.h 1970-01-01 01:00:00.000000000 +0100
|
||||
+++ linux.dev/drivers/mtd/devices/spiflash.h 2006-12-15 06:59:43.000000000 +0100
|
||||
@@ -0,0 +1,124 @@
|
||||
+/*
|
||||
+ * SPI Flash Memory support header file.
|
||||
+ *
|
||||
+ * $Id: //depot/sw/releases/linuxsrc/src/kernels/mips-linux-2.4.25/drivers/mtd/devices/spiflash.h#3 $
|
||||
+ *
|
||||
+ *
|
||||
+ * Copyright (c) 2005, Atheros Communications Inc.
|
||||
+ * Copyright (C) 2006 FON Technology, SL.
|
||||
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
|
||||
+ *
|
||||
+ * This code is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License version 2 as
|
||||
+ * published by the Free Software Foundation.
|
||||
+ *
|
||||
+ */
|
||||
+#define FLASH_1MB 1
|
||||
+#define FLASH_2MB 2
|
||||
+#define FLASH_4MB 3
|
||||
+#define FLASH_8MB 4
|
||||
+#define MAX_FLASH 5
|
||||
+
|
||||
+#define STM_PAGE_SIZE 256
|
||||
+
|
||||
+#define SPI_WRITE_ENABLE 0
|
||||
+#define SPI_WRITE_DISABLE 1
|
||||
+#define SPI_RD_STATUS 2
|
||||
+#define SPI_WR_STATUS 3
|
||||
+#define SPI_RD_DATA 4
|
||||
+#define SPI_FAST_RD_DATA 5
|
||||
+#define SPI_PAGE_PROGRAM 6
|
||||
+#define SPI_SECTOR_ERASE 7
|
||||
+#define SPI_BULK_ERASE 8
|
||||
+#define SPI_DEEP_PWRDOWN 9
|
||||
+#define SPI_RD_SIG 10
|
||||
+#define SPI_MAX_OPCODES 11
|
||||
+
|
||||
+#define SFI_WRITE_BUFFER_SIZE 4
|
||||
+#define SFI_FLASH_ADDR_MASK 0x00ffffff
|
||||
+
|
||||
+#define STM_8MBIT_SIGNATURE 0x13
|
||||
+#define STM_M25P80_BYTE_COUNT 1048576
|
||||
+#define STM_M25P80_SECTOR_COUNT 16
|
||||
+#define STM_M25P80_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_16MBIT_SIGNATURE 0x14
|
||||
+#define STM_M25P16_BYTE_COUNT 2097152
|
||||
+#define STM_M25P16_SECTOR_COUNT 32
|
||||
+#define STM_M25P16_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_32MBIT_SIGNATURE 0x15
|
||||
+#define STM_M25P32_BYTE_COUNT 4194304
|
||||
+#define STM_M25P32_SECTOR_COUNT 64
|
||||
+#define STM_M25P32_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_64MBIT_SIGNATURE 0x16
|
||||
+#define STM_M25P64_BYTE_COUNT 8388608
|
||||
+#define STM_M25P64_SECTOR_COUNT 128
|
||||
+#define STM_M25P64_SECTOR_SIZE 0x10000
|
||||
+
|
||||
+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
|
||||
+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
|
||||
+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
|
||||
+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
|
||||
+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
|
||||
+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
|
||||
+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
|
||||
+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
|
||||
+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
|
||||
+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
|
||||
+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
|
||||
+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
|
||||
+
|
||||
+/*
|
||||
+ * ST Microelectronics Opcodes for Serial Flash
|
||||
+ */
|
||||
+
|
||||
+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
|
||||
+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
|
||||
+#define STM_OP_RD_STATUS 0x05 /* Read Status */
|
||||
+#define STM_OP_WR_STATUS 0x01 /* Write Status */
|
||||
+#define STM_OP_RD_DATA 0x03 /* Read Data */
|
||||
+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
|
||||
+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
|
||||
+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
|
||||
+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
|
||||
+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
|
||||
+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
|
||||
+
|
||||
+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
|
||||
+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
|
||||
+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
|
||||
+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
|
||||
+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
|
||||
+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
|
||||
+
|
||||
+/*
|
||||
+ * SPI Flash Interface Registers
|
||||
+ */
|
||||
+#define AR531XPLUS_SPI_READ 0x08000000
|
||||
+#define AR531XPLUS_SPI_MMR 0x11300000
|
||||
+#define AR531XPLUS_SPI_MMR_SIZE 12
|
||||
+
|
||||
+#define AR531XPLUS_SPI_CTL 0x00
|
||||
+#define AR531XPLUS_SPI_OPCODE 0x04
|
||||
+#define AR531XPLUS_SPI_DATA 0x08
|
||||
+
|
||||
+#define SPI_FLASH_READ AR531XPLUS_SPI_READ
|
||||
+#define SPI_FLASH_MMR AR531XPLUS_SPI_MMR
|
||||
+#define SPI_FLASH_MMR_SIZE AR531XPLUS_SPI_MMR_SIZE
|
||||
+#define SPI_FLASH_CTL AR531XPLUS_SPI_CTL
|
||||
+#define SPI_FLASH_OPCODE AR531XPLUS_SPI_OPCODE
|
||||
+#define SPI_FLASH_DATA AR531XPLUS_SPI_DATA
|
||||
+
|
||||
+#define SPI_CTL_START 0x00000100
|
||||
+#define SPI_CTL_BUSY 0x00010000
|
||||
+#define SPI_CTL_TXCNT_MASK 0x0000000f
|
||||
+#define SPI_CTL_RXCNT_MASK 0x000000f0
|
||||
+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
|
||||
+#define SPI_CTL_SIZE_MASK 0x00060000
|
||||
+
|
||||
+#define SPI_CTL_CLK_SEL_MASK 0x03000000
|
||||
+#define SPI_OPCODE_MASK 0x000000ff
|
||||
+
|
||||
+#define SPI_STATUS_WIP STM_STATUS_WIP
|
||||
|
||||
@ -0,0 +1,13 @@
|
||||
diff -urN linux.old/drivers/net/wireless/Kconfig linux.dev/drivers/net/wireless/Kconfig
|
||||
--- linux.old/drivers/net/wireless/Kconfig 2006-11-29 22:57:37.000000000 +0100
|
||||
+++ linux.dev/drivers/net/wireless/Kconfig 2006-12-15 00:03:15.000000000 +0100
|
||||
@@ -545,7 +545,7 @@
|
||||
# yes, this works even when no drivers are selected
|
||||
config NET_WIRELESS
|
||||
bool
|
||||
- depends on NET_RADIO && (ISA || PCI || PPC_PMAC || PCMCIA)
|
||||
+ depends on NET_RADIO && (ISA || PCI || PPC_PMAC || PCMCIA || AR531X)
|
||||
default y
|
||||
|
||||
endmenu
|
||||
|
||||
2072
target/linux/atheros-2.6/patches/130-ar2313_ethernet.patch
Normal file
2072
target/linux/atheros-2.6/patches/130-ar2313_ethernet.patch
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,24 @@
|
||||
diff -urN linux.old/drivers/mtd/redboot.c linux.dev/drivers/mtd/redboot.c
|
||||
--- linux.old/drivers/mtd/redboot.c 2006-12-14 23:53:29.000000000 +0100
|
||||
+++ linux.dev/drivers/mtd/redboot.c 2006-12-16 04:23:42.000000000 +0100
|
||||
@@ -64,6 +64,7 @@
|
||||
if (!buf)
|
||||
return -ENOMEM;
|
||||
|
||||
+restart:
|
||||
if ( directory < 0 )
|
||||
offset = master->size + directory*master->erasesize;
|
||||
else
|
||||
@@ -139,6 +140,11 @@
|
||||
}
|
||||
if (i == numslots) {
|
||||
/* Didn't find it */
|
||||
+ if (offset + master->erasesize < master->size) {
|
||||
+ /* not at the end of the flash yet, maybe next block :) */
|
||||
+ directory++;
|
||||
+ goto restart;
|
||||
+ }
|
||||
printk(KERN_NOTICE "No RedBoot partition table detected in %s\n",
|
||||
master->name);
|
||||
ret = 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user