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@ -5,10 +5,10 @@
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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+#include <linux/ssb/ssb_driver_gige.h>
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#if IS_ENABLED(CONFIG_HWMON)
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#include <linux/hwmon.h>
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#include <linux/hwmon-sysfs.h>
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@@ -253,6 +254,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
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@@ -251,6 +252,7 @@ static DEFINE_PCI_DEVICE_TABLE(tg3_pci_t
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
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@ -16,7 +16,7 @@
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
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{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
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@@ -535,7 +537,9 @@ static void _tw32_flush(struct tg3 *tp,
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@@ -533,7 +535,9 @@ static void _tw32_flush(struct tg3 *tp,
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static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
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{
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tp->write32_mbox(tp, off, val);
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@ -27,7 +27,7 @@
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tp->read32_mbox(tp, off);
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}
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@@ -545,7 +549,8 @@ static void tg3_write32_tx_mbox(struct t
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@@ -543,7 +547,8 @@ static void tg3_write32_tx_mbox(struct t
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writel(val, mbox);
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if (tg3_flag(tp, TXD_MBOX_HWBUG))
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writel(val, mbox);
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@ -37,7 +37,7 @@
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readl(mbox);
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}
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@@ -1052,7 +1057,8 @@ static void tg3_switch_clocks(struct tg3
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@@ -1050,7 +1055,8 @@ static void tg3_switch_clocks(struct tg3
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#define PHY_BUSY_LOOPS 5000
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@ -47,7 +47,7 @@
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{
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u32 frame_val;
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unsigned int loops;
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@@ -1068,7 +1074,7 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -1066,7 +1072,7 @@ static int tg3_readphy(struct tg3 *tp, i
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*val = 0x0;
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@ -56,7 +56,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -1105,7 +1111,13 @@ static int tg3_readphy(struct tg3 *tp, i
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@@ -1103,7 +1109,13 @@ static int tg3_readphy(struct tg3 *tp, i
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return ret;
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}
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@ -71,7 +71,7 @@
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{
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u32 frame_val;
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unsigned int loops;
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@@ -1123,7 +1135,7 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1121,7 +1133,7 @@ static int tg3_writephy(struct tg3 *tp,
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tg3_ape_lock(tp, tp->phy_ape_lock);
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@ -80,7 +80,7 @@
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MI_COM_PHY_ADDR_MASK);
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frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
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MI_COM_REG_ADDR_MASK);
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@@ -1158,6 +1170,11 @@ static int tg3_writephy(struct tg3 *tp,
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@@ -1156,6 +1168,11 @@ static int tg3_writephy(struct tg3 *tp,
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return ret;
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}
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@ -92,7 +92,7 @@
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static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
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{
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int err;
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@@ -1730,6 +1747,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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@@ -1728,6 +1745,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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int i;
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u32 val;
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@ -104,7 +104,7 @@
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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/* Wait up to 20ms for init done. */
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for (i = 0; i < 200; i++) {
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@@ -3312,6 +3334,8 @@ static int tg3_nvram_write_block(struct
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@@ -3310,6 +3332,8 @@ static int tg3_nvram_write_block(struct
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{
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int ret;
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@ -113,7 +113,7 @@
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if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
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tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
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~GRC_LCLCTRL_GPIO_OUTPUT1);
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@@ -3387,6 +3411,11 @@ static int tg3_halt_cpu(struct tg3 *tp,
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@@ -3385,6 +3409,11 @@ static int tg3_halt_cpu(struct tg3 *tp,
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tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
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udelay(10);
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} else {
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@ -125,7 +125,7 @@
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for (i = 0; i < 10000; i++) {
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tw32(offset + CPU_STATE, 0xffffffff);
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tw32(offset + CPU_MODE, CPU_MODE_HALT);
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@@ -3401,9 +3430,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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@@ -3399,9 +3428,12 @@ static int tg3_halt_cpu(struct tg3 *tp,
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return -ENODEV;
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}
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@ -141,7 +141,7 @@
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return 0;
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}
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@@ -3466,6 +3498,11 @@ static int tg3_load_5701_a0_firmware_fix
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@@ -3464,6 +3496,11 @@ static int tg3_load_5701_a0_firmware_fix
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const __be32 *fw_data;
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int err, i;
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@ -153,7 +153,7 @@
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fw_data = (void *)tp->fw->data;
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/* Firmware blob starts with version numbers, followed by
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@@ -3522,6 +3559,11 @@ static int tg3_load_tso_firmware(struct
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@@ -3520,6 +3557,11 @@ static int tg3_load_tso_firmware(struct
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unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
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int err, i;
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@ -165,7 +165,7 @@
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if (tg3_flag(tp, HW_TSO_1) ||
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tg3_flag(tp, HW_TSO_2) ||
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tg3_flag(tp, HW_TSO_3))
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@@ -3862,8 +3904,9 @@ static int tg3_power_down_prepare(struct
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@@ -3860,8 +3902,9 @@ static int tg3_power_down_prepare(struct
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tg3_frob_aux_power(tp, true);
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/* Workaround for unstable PLL clock */
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@ -177,7 +177,7 @@
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u32 val = tr32(0x7d00);
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val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
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@@ -4365,6 +4408,14 @@ relink:
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@@ -4363,6 +4406,14 @@ relink:
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if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
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tg3_phy_copper_begin(tp);
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@ -192,7 +192,7 @@
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tg3_readphy(tp, MII_BMSR, &bmsr);
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if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
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(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
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@@ -4383,6 +4434,26 @@ relink:
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@@ -4381,6 +4432,26 @@ relink:
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else
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tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
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@ -219,7 +219,7 @@
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tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
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if (tp->link_config.active_duplex == DUPLEX_HALF)
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tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
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@@ -8110,6 +8181,14 @@ static int tg3_chip_reset(struct tg3 *tp
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@@ -8108,6 +8179,14 @@ static int tg3_chip_reset(struct tg3 *tp
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tw32(0x5000, 0x400);
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}
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@ -234,7 +234,7 @@
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tw32(GRC_MODE, tp->grc_mode);
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if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
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@@ -9729,6 +9808,11 @@ static void tg3_timer(unsigned long __op
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@@ -9720,6 +9799,11 @@ static void tg3_timer(unsigned long __op
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tg3_flag(tp, 57765_CLASS))
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tg3_chk_missed_msi(tp);
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@ -246,7 +246,7 @@
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if (!tg3_flag(tp, TAGGED_STATUS)) {
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/* All of this garbage is because when using non-tagged
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* IRQ status the mailbox/status_block protocol the chip
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@@ -11424,6 +11508,11 @@ static int tg3_test_nvram(struct tg3 *tp
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@@ -11415,6 +11499,11 @@ static int tg3_test_nvram(struct tg3 *tp
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if (tg3_flag(tp, NO_NVRAM))
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return 0;
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@ -258,7 +258,7 @@
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if (tg3_nvram_read(tp, 0, &magic) != 0)
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return -EIO;
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@@ -12392,11 +12481,12 @@ static int tg3_ioctl(struct net_device *
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@@ -12383,11 +12472,12 @@ static int tg3_ioctl(struct net_device *
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if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
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break; /* We have no PHY */
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@ -273,7 +273,7 @@
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spin_unlock_bh(&tp->lock);
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data->val_out = mii_regval;
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@@ -12408,11 +12498,12 @@ static int tg3_ioctl(struct net_device *
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@@ -12399,11 +12489,12 @@ static int tg3_ioctl(struct net_device *
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if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
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break; /* We have no PHY */
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@ -288,7 +288,7 @@
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spin_unlock_bh(&tp->lock);
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return err;
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@@ -13260,6 +13351,13 @@ static void __devinit tg3_get_5720_nvram
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@@ -13251,6 +13342,13 @@ static void __devinit tg3_get_5720_nvram
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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@ -302,7 +302,7 @@
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tw32_f(GRC_EEPROM_ADDR,
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(EEPROM_ADDR_FSM_RESET |
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(EEPROM_DEFAULT_CLOCK_PERIOD <<
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@@ -13752,10 +13850,19 @@ static int __devinit tg3_phy_probe(struc
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@@ -13743,10 +13841,19 @@ static int __devinit tg3_phy_probe(struc
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* subsys device table.
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*/
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p = tg3_lookup_by_subsys(tp);
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@ -324,7 +324,7 @@
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if (!tp->phy_id ||
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tp->phy_id == TG3_PHY_ID_BCM8002)
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tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
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@@ -14765,6 +14872,11 @@ static int __devinit tg3_get_invariants(
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@@ -14756,6 +14863,11 @@ static int __devinit tg3_get_invariants(
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}
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}
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@ -336,7 +336,7 @@
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/* Get eeprom hw config before calling tg3_set_power_state().
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* In particular, the TG3_FLAG_IS_NIC flag must be
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* determined before calling tg3_set_power_state() so that
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@@ -15174,6 +15286,10 @@ static int __devinit tg3_get_device_addr
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@@ -15165,6 +15277,10 @@ static int __devinit tg3_get_device_addr
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}
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if (!is_valid_ether_addr(&dev->dev_addr[0])) {
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@ -347,7 +347,7 @@
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#ifdef CONFIG_SPARC
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if (!tg3_get_default_macaddr_sparc(tp))
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return 0;
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@@ -15458,7 +15574,8 @@ static int __devinit tg3_test_dma(struct
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@@ -15449,7 +15565,8 @@ static int __devinit tg3_test_dma(struct
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if (tg3_flag(tp, 40BIT_DMA_BUG) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
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tp->dma_rwctrl |= 0x8000;
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@ -357,7 +357,7 @@
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tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
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@@ -15820,6 +15937,17 @@ static int __devinit tg3_init_one(struct
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@@ -15811,6 +15928,17 @@ static int __devinit tg3_init_one(struct
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tp->msg_enable = tg3_debug;
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else
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tp->msg_enable = TG3_DEF_MSG_ENABLE;
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