remove unneeded patches
SVN-Revision: 23774
This commit is contained in:
Imre Kaloz
parent
6e3a7fea20
commit
3b1eb0f07c
@ -1,154 +0,0 @@
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -435,7 +435,6 @@ config ARCH_IXP4XX
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select CPU_XSCALE
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select GENERIC_GPIO
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select GENERIC_CLOCKEVENTS
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- select DMABOUNCE if PCI
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help
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Support for Intel's IXP4XX (XScale) family of processors.
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--- a/arch/arm/mach-ixp4xx/Kconfig
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+++ b/arch/arm/mach-ixp4xx/Kconfig
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@@ -199,6 +199,43 @@ config IXP4XX_INDIRECT_PCI
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need to use the indirect method instead. If you don't know
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what you need, leave this option unselected.
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+config IXP4XX_LEGACY_DMABOUNCE
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+ bool "Legacy PCI DMA bounce support"
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+ depends on PCI
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+ default n
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+ select DMABOUNCE
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+ help
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+ The IXP4xx is limited to a 64MB window for PCI DMA, which
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+ requires that PCI accesses >= 64MB are bounced via buffers
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+ below 64MB.
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+
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+ The kernel has traditionally handled this issue by using ARM
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+ specific DMA bounce support code for all accesses >= 64MB.
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+ That code causes problems of its own, so it is desirable to
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+ disable it.
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+
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+ Enabling this option makes IXP4xx continue to use the problematic
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+ ARM DMA bounce code. Disabling this option makes IXP4xx use the
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+ kernel's generic bounce code.
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+
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+ Say 'N'.
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+
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+config IXP4XX_ZONE_DMA
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+ bool "Support > 64MB RAM"
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+ depends on !IXP4XX_LEGACY_DMABOUNCE
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+ default y
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+ select ZONE_DMA
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+ help
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+ The IXP4xx is limited to a 64MB window for PCI DMA, which
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+ requires that PCI accesses above 64MB are bounced via buffers
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+ below 64MB.
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+
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+ Disabling this option allows you to omit the support code for
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+ DMA-able memory allocations and DMA bouncing, but the kernel
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+ will then not work properly if more than 64MB of RAM is present.
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+
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+ Say 'Y' unless your platform is limited to <= 64MB of RAM.
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+
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config IXP4XX_QMGR
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tristate "IXP4xx Queue Manager support"
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help
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--- a/arch/arm/mach-ixp4xx/common-pci.c
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+++ b/arch/arm/mach-ixp4xx/common-pci.c
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@@ -321,27 +321,33 @@ static int abort_handler(unsigned long a
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*/
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static int ixp4xx_pci_platform_notify(struct device *dev)
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{
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- if(dev->bus == &pci_bus_type) {
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- *dev->dma_mask = SZ_64M - 1;
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+ if (dev->bus == &pci_bus_type) {
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+ *dev->dma_mask = SZ_64M - 1;
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dev->coherent_dma_mask = SZ_64M - 1;
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+#ifdef CONFIG_DMABOUNCE
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dmabounce_register_dev(dev, 2048, 4096);
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+#endif
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}
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return 0;
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}
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static int ixp4xx_pci_platform_notify_remove(struct device *dev)
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{
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- if(dev->bus == &pci_bus_type) {
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+#ifdef CONFIG_DMABOUNCE
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+ if (dev->bus == &pci_bus_type)
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dmabounce_unregister_dev(dev);
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- }
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+#endif
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return 0;
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}
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-int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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+#ifdef CONFIG_DMABOUNCE
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+int dma_needs_bounce_2(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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- return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
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+ return (dev->bus == &pci_bus_type ) && ((dma_addr + size) > SZ_64M);
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}
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+#endif
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+#ifdef CONFIG_ZONE_DMA
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/*
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* Only first 64MB of memory can be accessed via PCI.
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* We use GFP_DMA to allocate safe buffers to do map/unmap.
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@@ -364,6 +370,7 @@ void __init ixp4xx_adjust_zones(unsigned
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zhole_size[1] = zhole_size[0];
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zhole_size[0] = 0;
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}
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+#endif
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void __init ixp4xx_pci_preinit(void)
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{
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--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
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+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
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@@ -16,10 +16,12 @@
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#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
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+#ifdef CONFIG_ZONE_DMA
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void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
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#define arch_adjust_zones(size, holes) \
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ixp4xx_adjust_zones(size, holes)
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+#endif
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#define ISA_DMA_THRESHOLD (SZ_64M - 1)
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#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
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--- a/arch/arm/common/dmabounce.c
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+++ b/arch/arm/common/dmabounce.c
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@@ -30,6 +30,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/list.h>
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+#include <linux/pci.h>
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#include <linux/scatterlist.h>
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#include <asm/cacheflush.h>
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@@ -248,7 +249,13 @@ static inline dma_addr_t map_single(stru
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needs_bounce = (dma_addr | (dma_addr + size - 1)) & ~mask;
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}
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- if (device_info && (needs_bounce || dma_needs_bounce(dev, dma_addr, size))) {
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+#ifdef CONFIG_DMABOUNCE
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+int dma_needs_bounce_2(struct device *dev, dma_addr_t dma_addr, size_t size)
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+{
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+ return (dev->bus == &pci_bus_type ) && ((dma_addr + size) > SZ_64M);
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+}
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+
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+ if (device_info && (needs_bounce || dma_needs_bounce_2(dev, dma_addr, size))) {
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struct safe_buffer *buf;
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buf = alloc_safe_buffer(device_info, ptr, size, dir);
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@@ -282,6 +289,7 @@ static inline dma_addr_t map_single(stru
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return dma_addr;
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}
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+#endif
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static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction dir)
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@ -1,12 +0,0 @@
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--- a/arch/arm/mm/dma-mapping.c
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+++ b/arch/arm/mm/dma-mapping.c
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@@ -381,7 +381,8 @@ EXPORT_SYMBOL(dma_mmap_writecombine);
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*/
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void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
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{
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- WARN_ON(irqs_disabled());
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+ if (irqs_disabled()) /* don't want stack dumps for these! */
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+ printk("WARNING: at %s:%d %s()\n", __FILE__, __LINE__, __FUNCTION__);
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if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
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return;
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@ -1,33 +0,0 @@
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--- a/arch/arm/kernel/setup.c
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+++ b/arch/arm/kernel/setup.c
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@@ -323,12 +323,13 @@ static void __init setup_processor(void)
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void cpu_init(void)
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{
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unsigned int cpu = smp_processor_id();
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- struct stack *stk = &stacks[cpu];
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+ struct stack *stk;
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if (cpu >= NR_CPUS) {
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printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
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BUG();
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}
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+ stk = &stacks[cpu];
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/*
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* Define the placement constraint for the inline asm directive below.
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@@ -387,13 +388,14 @@ static struct machine_desc * __init setu
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static int __init arm_add_memory(unsigned long start, unsigned long size)
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{
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- struct membank *bank = &meminfo.bank[meminfo.nr_banks];
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+ struct membank *bank;
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if (meminfo.nr_banks >= NR_BANKS) {
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printk(KERN_CRIT "NR_BANKS too low, "
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"ignoring memory at %#lx\n", start);
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return -EINVAL;
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}
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+ bank = &meminfo.bank[meminfo.nr_banks];
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/*
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* Ensure that start/size are aligned to a page boundary.
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