ar71xx: add initial support for the AR934x SoCs
Signed-off-by: Jaiganesh Narayanan <jnarayanan@atheros.com> SVN-Revision: 26509
This commit is contained in:
Gabor Juhos
parent
40d6cd6c16
commit
3b209880bc
@ -1,10 +1,12 @@
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/*
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* Atheros AR71xx SoC specific setup
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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@ -39,6 +41,9 @@ EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
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u32 ar71xx_ddr_freq;
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EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
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u32 ar934x_ref_freq;
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EXPORT_SYMBOL_GPL(ar934x_ref_freq);
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enum ar71xx_soc_type ar71xx_soc;
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EXPORT_SYMBOL_GPL(ar71xx_soc);
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@ -141,6 +146,27 @@ static void __init ar71xx_detect_sys_type(void)
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}
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break;
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case REV_ID_MAJOR_AR9341:
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ar71xx_soc = AR71XX_SOC_AR9341;
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chip = "9341";
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rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) &
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AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9342:
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ar71xx_soc = AR71XX_SOC_AR9342;
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chip = "9342";
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rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) &
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AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9344:
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ar71xx_soc = AR71XX_SOC_AR9344;
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chip = "9344";
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rev = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID) &
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AR934X_REV_ID_REVISION_MASK;
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break;
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default:
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panic("ar71xx: unknown chip id:0x%08x\n", id);
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}
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@ -148,6 +174,44 @@ static void __init ar71xx_detect_sys_type(void)
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sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
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}
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static void __init ar934x_detect_sys_frequency(void)
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{
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, ref, postdiv;
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if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
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ref = (40 * 1000000);
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else
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ref = (25 * 1000000);
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ar934x_ref_freq = ref;
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clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
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pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
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out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
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ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
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nint = AR934X_CPU_PLL_CFG_NINT_GET(pll);
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frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
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postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
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ar71xx_cpu_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
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out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
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ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
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nint = AR934X_DDR_PLL_CFG_NINT_GET(pll);
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frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
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postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
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ar71xx_ddr_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
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postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
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if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
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ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
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} else {
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ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
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}
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}
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static void __init ar91xx_detect_sys_frequency(void)
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{
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u32 pll;
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@ -232,6 +296,11 @@ static void __init detect_sys_frequency(void)
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ar91xx_detect_sys_frequency();
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break;
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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ar934x_detect_sys_frequency();
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break;
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default:
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BUG();
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}
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@ -1,10 +1,12 @@
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/*
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* Atheros AR71xx SoC specific definitions
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.15 BSP
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* Parts of this file are based on Atheros 2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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@ -105,6 +107,7 @@
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extern u32 ar71xx_ahb_freq;
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extern u32 ar71xx_cpu_freq;
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extern u32 ar71xx_ddr_freq;
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extern u32 ar934x_ref_freq;
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enum ar71xx_soc_type {
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AR71XX_SOC_UNKNOWN,
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@ -115,7 +118,10 @@ enum ar71xx_soc_type {
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AR71XX_SOC_AR7241,
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AR71XX_SOC_AR7242,
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AR71XX_SOC_AR9130,
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AR71XX_SOC_AR9132
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AR71XX_SOC_AR9132,
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AR71XX_SOC_AR9341,
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AR71XX_SOC_AR9342,
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AR71XX_SOC_AR9344,
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};
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extern enum ar71xx_soc_type ar71xx_soc;
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@ -167,6 +173,167 @@ extern enum ar71xx_soc_type ar71xx_soc;
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#define AR91XX_ETH0_PLL_SHIFT 20
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#define AR91XX_ETH1_PLL_SHIFT 22
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#define AR934X_PLL_REG_CPU_CONFIG 0x00
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#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
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#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
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#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19
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#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000
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#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \
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AR934X_CPU_PLL_CFG_OUTDIV_LSB)
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#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25
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#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23
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#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000
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#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \
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AR934X_DDR_PLL_CFG_OUTDIV_LSB)
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#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \
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AR934X_DDR_PLL_CFG_OUTDIV_MASK)
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#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16
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#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12
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#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000
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#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \
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AR934X_CPU_PLL_CFG_REFDIV_LSB)
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#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \
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(((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \
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AR934X_CPU_PLL_CFG_REFDIV_MASK)
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#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
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#define AR934X_CPU_PLL_CFG_NINT_MSB 11
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#define AR934X_CPU_PLL_CFG_NINT_LSB 6
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#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0
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#define AR934X_CPU_PLL_CFG_NINT_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \
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AR934X_CPU_PLL_CFG_NINT_LSB)
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#define AR934X_CPU_PLL_CFG_NINT_SET(x) \
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(((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \
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AR934X_CPU_PLL_CFG_NINT_MASK)
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#define AR934X_CPU_PLL_CFG_NINT_RESET 20
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#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5
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#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0
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#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f
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#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \
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(((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \
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AR934X_CPU_PLL_CFG_NFRAC_LSB)
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#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \
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(((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \
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AR934X_CPU_PLL_CFG_NFRAC_MASK)
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#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20
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#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16
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#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000
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#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \
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AR934X_DDR_PLL_CFG_REFDIV_LSB)
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#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \
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AR934X_DDR_PLL_CFG_REFDIV_MASK)
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#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
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#define AR934X_DDR_PLL_CFG_NINT_MSB 15
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#define AR934X_DDR_PLL_CFG_NINT_LSB 10
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#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00
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#define AR934X_DDR_PLL_CFG_NINT_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \
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AR934X_DDR_PLL_CFG_NINT_LSB)
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#define AR934X_DDR_PLL_CFG_NINT_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \
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AR934X_DDR_PLL_CFG_NINT_MASK)
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#define AR934X_DDR_PLL_CFG_NINT_RESET 20
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#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9
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#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0
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#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff
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#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \
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(((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \
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AR934X_DDR_PLL_CFG_NFRAC_LSB)
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#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \
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(((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \
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AR934X_DDR_PLL_CFG_NFRAC_MASK)
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#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \
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(((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \
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AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \
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(((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \
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AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
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#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \
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(((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \
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AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \
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(((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \
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AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
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#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0
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#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9
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#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5
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#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0
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#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \
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(((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \
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AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
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#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \
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(((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \
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AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
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#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0
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#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24
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#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24
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#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
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#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \
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(((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
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AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
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#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \
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(((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
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AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
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#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
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extern void __iomem *ar71xx_pll_base;
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static inline void ar71xx_pll_wr(unsigned reg, u32 val)
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@ -385,6 +552,11 @@ void ar71xx_ddr_flush(u32 reg);
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#define AR724X_RESET_REG_RESET_MODULE 0x1c
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#define AR934X_RESET_REG_RESET_MODULE 0x1c
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#define AR934X_RESET_REG_BOOTSTRAP 0xb0
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/* 0 - 25MHz 1 - 40 MHz */
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#define AR934X_REF_CLK_40 (1 << 4)
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#define WDOG_CTRL_LAST_RESET BIT(31)
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#define WDOG_CTRL_ACTION_MASK 3
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#define WDOG_CTRL_ACTION_NONE 0 /* no action */
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@ -442,6 +614,9 @@ void ar71xx_ddr_flush(u32 reg);
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#define REV_ID_MAJOR_AR7240 0x00c0
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#define REV_ID_MAJOR_AR7241 0x0100
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#define REV_ID_MAJOR_AR7242 0x1100
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#define REV_ID_MAJOR_AR9341 0x0120
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#define REV_ID_MAJOR_AR9342 0x1120
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#define REV_ID_MAJOR_AR9344 0x2120
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#define AR71XX_REV_ID_MINOR_MASK 0x3
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#define AR71XX_REV_ID_MINOR_AR7130 0x0
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@ -458,6 +633,8 @@ void ar71xx_ddr_flush(u32 reg);
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#define AR724X_REV_ID_REVISION_MASK 0x3
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#define AR934X_REV_ID_REVISION_MASK 0xf
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extern void __iomem *ar71xx_reset_base;
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static inline void ar71xx_reset_wr(unsigned reg, u32 val)
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