uboot-lantiq
fix arv752DPW and add arv7525PW SVN-Revision: 27664
This commit is contained in:
John Crispin
parent
c0c7c82a2f
commit
4da4c491a6
@ -61,6 +61,9 @@ Package/uboot-lantiq-arv4520PW_brnboot=$(call Package/uboot-lantiq-template,arv4
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Package/uboot-lantiq-arv4525PW_flash=$(call Package/uboot-lantiq-template,arv4525PW_flash,NOR)
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Package/uboot-lantiq-arv4525PW_ramboot=$(call Package/uboot-lantiq-template,arv4525PW_ramboot,RAM)
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Package/uboot-lantiq-arv4525PW_brnboot=$(call Package/uboot-lantiq-template,arv4525PW_brnboot,BRN)
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Package/uboot-lantiq-arv7525PW_flash=$(call Package/uboot-lantiq-template,arv7525PW_flash,NOR)
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Package/uboot-lantiq-arv7525PW_ramboot=$(call Package/uboot-lantiq-template,arv7525PW_ramboot,RAM)
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Package/uboot-lantiq-arv7525PW_brnboot=$(call Package/uboot-lantiq-template,arv7525PW_brnboot,BRN)
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Package/uboot-lantiq-arv452CPW_flash=$(call Package/uboot-lantiq-template,arv452CPW_flash,NOR)
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Package/uboot-lantiq-arv452CPW_ramboot=$(call Package/uboot-lantiq-template,arv452CPW_ramboot,RAM)
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Package/uboot-lantiq-arv452CPW_brnboot=$(call Package/uboot-lantiq-template,arv452CPW_brnboot,BRN)
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@ -75,6 +78,7 @@ DDR_CONFIG_arv3527P_ramboot:=arcadyan_psc166_32
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DDR_CONFIG_arv4518PW_ramboot:=arcadyan_psc166_64
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DDR_CONFIG_arv4520PW_ramboot:=arcadyan_psc166_32
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DDR_CONFIG_arv4525PW_ramboot:=arcadyan_psc166_32
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DDR_CONFIG_arv7525PW_ramboot:=arcadyan_psc166_32
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DDR_CONFIG_arv452CPW_ramboot:=arcadyan_psc166_32
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DDR_CONFIG_arv752DPW_ramboot:=arcadyan_psc166_64
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DDR_CONFIG_arv752DPW22_ramboot:=arcadyan_psc166_64
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@ -153,6 +157,9 @@ $(eval $(call BuildPackage,uboot-lantiq-arv4520PW_ramboot))
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$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_flash))
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$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_brnboot))
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$(eval $(call BuildPackage,uboot-lantiq-arv4525PW_ramboot))
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$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_flash))
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$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_brnboot))
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$(eval $(call BuildPackage,uboot-lantiq-arv7525PW_ramboot))
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$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_flash))
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$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_brnboot))
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$(eval $(call BuildPackage,uboot-lantiq-arv452CPW_ramboot))
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@ -312,6 +312,107 @@ static int external_switch_rtl8306(void)
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}
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#endif
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#ifdef CONFIG_RTL8306G_SWITCH
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#define ID_RTL8306 0x5988
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static int external_switch_rtl8306G(void)
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{
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unsigned short chipid,val;
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int i;
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static char * const name = "lq_cpe_eth";
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unsigned int chipid2, chipver, chiptype;
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char str[128];
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int cpu_mask = 1 << 5;
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udelay(100000);
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puts("\nsearching for rtl8306 switch ... ");
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if (miiphy_read(name, 4, 30, &chipid) == 0) {
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if (chipid == ID_RTL8306) {
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puts("found\nReset Hard\n");
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#ifdef CONFIG_ARV752DPW
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//gpio 19
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//reset reset ping to high
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*DANUBE_GPIO_P1_DIR |= 8;
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*DANUBE_GPIO_P1_OUT |= 8;
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udelay(500*1000);
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*DANUBE_GPIO_P1_OUT &= ~(8); // now low again for at least 10 ms
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udelay(500*1000);
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*DANUBE_GPIO_P1_OUT |= 8;
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udelay(500*1000);
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puts("Done\n");
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#endif
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/* set led mode */
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miiphy_write(name, 0, 0, 0x3100);
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miiphy_write(name, 0, 18, 0x7fff);
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miiphy_write(name, 0, 19, 0xffff);
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miiphy_write(name, 0, 22, 0x877f);
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miiphy_write(name, 0, 24, 0x0ed1);
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miiphy_write(name, 1, 0, 0x3100);
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miiphy_write(name, 1, 22, 0x877f);
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miiphy_write(name, 1, 24, 0x1ed2);
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miiphy_write(name, 2, 0, 0x3100);
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miiphy_write(name, 2, 22, 0x877f);
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miiphy_write(name, 2, 23, 0x0020);
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miiphy_write(name, 2, 24, 0x2ed4);
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miiphy_write(name, 3, 0, 0x3100);
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miiphy_write(name, 3, 22, 0x877f);
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miiphy_write(name, 3, 24, 0x3ed8);
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miiphy_write(name, 4, 0, 0x3100);
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miiphy_write(name, 4, 22, 0x877f);
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miiphy_write(name, 4, 24, 0x4edf);
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miiphy_write(name, 5, 0, 0x3100);
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miiphy_write(name, 6, 0, 0x2100);
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//important. enable phy 5 link status, for rmii
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miiphy_write(name, 6, 22, 0x873f);
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miiphy_write(name, 6, 24, 0x8eff);
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//disable ports
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for (i=0;i<5;i++) {
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miiphy_read(name, 0, 24, &val);
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val&=~(1<<10);
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val&=~(1<<11);
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miiphy_write(name, 0, 24, val);
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}
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puts("Reset Soft\n");
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miiphy_write(name,0 ,0 ,1<<15);
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for (i=0;i<1000;i++)
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{
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miiphy_read(name,0 ,0 ,&val);
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if (!(val&1<<15))
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break;
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udelay(1000);
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}
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if (i==1000)
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puts("Failed\n");
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else
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puts("Success\n");
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//enable ports egain
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for (i=0;i<5;i++) // enable ports
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{
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miiphy_read(name, 0, 24, &val);
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val|=(1<<10);
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val|=(1<<11);
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miiphy_write(name, 0, 24, val);
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}
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puts("\n");
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return 0;
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}
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puts("failed\n");
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}
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puts("\nno known switch found ... \n");
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return 0;
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}
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#endif
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#ifdef CONFIG_AR8216_SWITCH
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static int external_switch_ar8216(void)
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{
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@ -345,6 +446,10 @@ int board_eth_init(bd_t *bis)
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*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
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udelay(1000);
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#ifdef CONFIG_RTL8306G_SWITCH
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if (external_switch_rtl8306G()<0)
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return -1;
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#endif
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#ifdef CONFIG_RTL8306_SWITCH
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if (external_switch_rtl8306()<0)
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return -1;
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18
package/uboot-lantiq/files/include/configs/arv7525PW.h
Normal file
18
package/uboot-lantiq/files/include/configs/arv7525PW.h
Normal file
@ -0,0 +1,18 @@
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#ifndef __CONFIG_H_7525PW
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#define __CONFIG_H_7525PW
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#define CONFIG_ARV7525 1
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#define CONFIG_ARCADYAN "ARV7525PW"
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#define CONFIG_SYS_MAX_RAM 32*1024*1024
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#define CONFIG_USE_DDR_PSC_32 1
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#define CONFIG_SYS_PROMPT "ARV7525 => "
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#define CONFIG_BUTTON_PORT1
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#define CONFIG_BUTTON_PIN 13
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#define CONFIG_BUTTON_LEVEL 0
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#include "arcadyan-common.h"
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#endif
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@ -11,8 +11,6 @@
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#define CONFIG_RMII
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#define CONFIG_RTL8306G_SWITCH 1
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//#define CONFIG_EBU_GPIO 0x2
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#define CONFIG_SWITCH_PORT1
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#define CONFIG_SWITCH_PIN 3
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//#define CONFIG_BUTTON_PORT0
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//#define CONFIG_BUTTON_PIN 12
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@ -39,7 +39,7 @@
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SRCS := $(COBJS:.o=.c)
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--- a/Makefile
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+++ b/Makefile
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@@ -3414,6 +3414,40 @@
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@@ -3414,6 +3414,41 @@
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## MIPS32 ifxcpe
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#########################################################################
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@ -74,6 +74,7 @@
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+$(eval $(call arcadyan, arv4510PW%config))
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+$(eval $(call arcadyan, arv4518PW%config))
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+$(eval $(call arcadyan, arv7518PW%config))
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+$(eval $(call arcadyan, arv7525PW%config))
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+$(eval $(call arcadyan, arv752DPW%config))
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+$(eval $(call arcadyan, arv752DPW22%config))
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+
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