now that the gemini target is working, get rid of the obsolete and buggy storm target
SVN-Revision: 16274
This commit is contained in:
Imre Kaloz
parent
51ed99475f
commit
7f9fd5033c
@ -97,9 +97,6 @@ endif
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ifeq ($(ARCH),powerpc)
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HAL_TARGET:=powerpc-be-elf
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endif
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ifeq ($(BOARD),storm)
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HAL_TARGET:=armv4-le-elf$(if $(CONFIG_EABI_SUPPORT),gnueabi)
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endif
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ifeq ($(BOARD),gemini)
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HAL_TARGET:=armv4-le-elf$(if $(CONFIG_EABI_SUPPORT),gnueabi)
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endif
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@ -1,23 +0,0 @@
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#
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# Copyright (C) 2006-2008 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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ARCH:=arm
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BOARD:=storm
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BOARDNAME:=Storm SL3512
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FEATURES:=squashfs pci broken
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CFLAGS:=-Os -pipe -march=armv4 -mtune=arm9tdmi -funit-at-a-time
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LINUX_VERSION:=2.6.23.17
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include $(INCLUDE_DIR)/target.mk
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define Target/Description
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Build images for boards based on the Storm Semiconductor SL3512, eg. Wiligear WBD-111
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endef
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$(eval $(call BuildTarget))
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@ -1,221 +0,0 @@
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# CONFIG_AEABI is not set
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CONFIG_ALIGNMENT_TRAP=y
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# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_SL2312=y
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# CONFIG_ARCH_SUPPORTS_MSI is not set
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CONFIG_ARM=y
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# CONFIG_ARPD is not set
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# CONFIG_ARTHUR is not set
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# CONFIG_ATM is not set
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CONFIG_BASE_SMALL=0
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# CONFIG_BINFMT_AOUT is not set
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CONFIG_BITREVERSE=y
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# CONFIG_BLK_DEV_INITRD is not set
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# CONFIG_BONDING is not set
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CONFIG_BOUNCE=y
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# CONFIG_BRIDGE_NF_EBTABLES is not set
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# CONFIG_BSD_PROCESS_ACCT is not set
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# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
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# CONFIG_CIFS is not set
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# CONFIG_CLS_U32_PERF is not set
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CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,19200 mem=32M"
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CONFIG_CPU_32=y
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CONFIG_CPU_32v4=y
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CONFIG_CPU_ABRT_EV4=y
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CONFIG_CPU_CACHE_FA=y
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CONFIG_CPU_CACHE_VIVT=y
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CONFIG_CPU_COPY_FA=y
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CONFIG_CPU_CP15=y
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CONFIG_CPU_CP15_MMU=y
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# CONFIG_CPU_DCACHE_DISABLE is not set
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# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
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CONFIG_CPU_FA526=y
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CONFIG_CPU_FA_BTB=y
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# CONFIG_CPU_ICACHE_DISABLE is not set
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CONFIG_CPU_TLB_FA=y
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# CONFIG_CRC_ITU_T is not set
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CONFIG_DEBUG_BUGVERBOSE=y
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# CONFIG_DEBUG_DEVRES is not set
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# CONFIG_DEBUG_DRIVER is not set
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# CONFIG_DEBUG_ERRORS is not set
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# CONFIG_DEBUG_INFO is not set
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CONFIG_DEBUG_KERNEL=y
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# CONFIG_DEBUG_KOBJECT is not set
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# CONFIG_DEBUG_LIST is not set
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# CONFIG_DEBUG_LL is not set
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# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
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# CONFIG_DEBUG_LOCK_ALLOC is not set
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# CONFIG_DEBUG_MUTEXES is not set
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# CONFIG_DEBUG_SHIRQ is not set
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# CONFIG_DEBUG_SLAB is not set
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# CONFIG_DEBUG_SPINLOCK is not set
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# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
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# CONFIG_DEBUG_USER is not set
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# CONFIG_DEBUG_VM is not set
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# CONFIG_DEFAULT_DEADLINE is not set
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CONFIG_DEFAULT_IOSCHED="noop"
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CONFIG_DEFAULT_NOOP=y
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# CONFIG_DETECT_SOFTLOCKUP is not set
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CONFIG_DEVPORT=y
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# CONFIG_DM9000 is not set
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CONFIG_ELF_CORE=y
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CONFIG_ENABLE_MUST_CHECK=y
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# CONFIG_EPOLL is not set
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# CONFIG_EXT2_FS is not set
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# CONFIG_EXT3_FS is not set
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# CONFIG_FAULT_INJECTION is not set
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CONFIG_FORCED_INLINING=y
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# CONFIG_FPE_FASTFPE is not set
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# CONFIG_FPE_NWFPE is not set
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CONFIG_FRAME_POINTER=y
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# CONFIG_FUTEX is not set
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# CONFIG_FW_LOADER is not set
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CONFIG_GEMINI_GPIO_DEV=y
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# CONFIG_GEMINI_IPI is not set
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# CONFIG_GENERIC_CLOCKEVENTS is not set
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# CONFIG_GENERIC_GPIO is not set
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# CONFIG_GENERIC_TIME is not set
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# CONFIG_HAMRADIO is not set
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CONFIG_HARDIRQS_SW_RESEND=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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# CONFIG_HFSPLUS_FS is not set
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# CONFIG_HFS_FS is not set
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CONFIG_HW_RANDOM=y
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# CONFIG_I2C is not set
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# CONFIG_IDE is not set
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# CONFIG_IEEE80211 is not set
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# CONFIG_IFB is not set
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# CONFIG_IKCONFIG is not set
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# CONFIG_IMQ is not set
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# CONFIG_INET6_TUNNEL is not set
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# CONFIG_INET6_XFRM_TUNNEL is not set
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# CONFIG_INET_AH is not set
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# CONFIG_INET_DIAG is not set
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# CONFIG_INET_ESP is not set
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# CONFIG_INET_IPCOMP is not set
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# CONFIG_INET_TUNNEL is not set
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# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
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# CONFIG_INET_XFRM_MODE_TUNNEL is not set
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# CONFIG_INET_XFRM_TUNNEL is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IPSEC_NAT_TRAVERSAL is not set
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# CONFIG_IPV6 is not set
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CONFIG_IP_MROUTE=y
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CONFIG_IP_PIMSM_V1=y
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CONFIG_IP_PIMSM_V2=y
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# CONFIG_ISDN is not set
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# CONFIG_ISO9660_FS is not set
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# CONFIG_JFFS2_RTIME is not set
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# CONFIG_JFFS2_SUMMARY is not set
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CONFIG_KALLSYMS=y
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# CONFIG_KALLSYMS_ALL is not set
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# CONFIG_LLC2 is not set
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# CONFIG_LOCK_STAT is not set
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# CONFIG_MINIX_FS is not set
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# CONFIG_MISC_DEVICES is not set
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# CONFIG_MSDOS_FS is not set
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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CONFIG_MTD_CFI_GEOMETRY=y
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# CONFIG_MTD_CFI_I2 is not set
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# CONFIG_MTD_CFI_INTELEXT is not set
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# CONFIG_MTD_COMPLEX_MAPPINGS is not set
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# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
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# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
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CONFIG_MTD_REDBOOT_PARTS=y
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# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
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# CONFIG_MTD_SERIAL is not set
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CONFIG_MTD_SL2312_CFI=y
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# CONFIG_MTD_SL2312_SERIAL_ATMEL is not set
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# CONFIG_MTD_SL2312_SERIAL_ST is not set
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CONFIG_NETDEV_1000=y
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# CONFIG_NET_ACT_GACT is not set
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# CONFIG_NET_ACT_IPT is not set
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# CONFIG_NET_ACT_MIRRED is not set
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# CONFIG_NET_ACT_PEDIT is not set
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# CONFIG_NET_CLS_RSVP is not set
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# CONFIG_NET_CLS_RSVP6 is not set
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# CONFIG_NET_EMATCH is not set
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CONFIG_NET_GMAC=y
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# CONFIG_NET_IPGRE is not set
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# CONFIG_NET_IPIP is not set
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# CONFIG_NET_KEY is not set
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# CONFIG_NET_PCI is not set
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# CONFIG_NET_PKTGEN is not set
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# CONFIG_NET_SCH_DSMARK is not set
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# CONFIG_NET_SCH_ESFQ is not set
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# CONFIG_NET_SCH_GRED is not set
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# CONFIG_NET_SCH_HFSC is not set
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# CONFIG_NET_SCH_HTB is not set
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# CONFIG_NET_SCH_INGRESS is not set
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# CONFIG_NET_SCH_PRIO is not set
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# CONFIG_NET_SCH_RED is not set
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# CONFIG_NET_SCH_RR is not set
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# CONFIG_NET_SCH_SFQ is not set
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# CONFIG_NET_SCH_TBF is not set
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# CONFIG_NET_SCH_TEQL is not set
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# CONFIG_NET_SL2312 is not set
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CONFIG_NET_SL351X=y
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# CONFIG_NET_VENDOR_3COM is not set
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# CONFIG_NEW_LEDS is not set
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# CONFIG_NFSD is not set
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# CONFIG_NFS_FS is not set
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CONFIG_NF_CONNTRACK=y
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# CONFIG_NLS is not set
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# CONFIG_NO_IDLE_HZ is not set
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# CONFIG_NO_IOPORT is not set
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# CONFIG_NVRAM is not set
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# CONFIG_OUTER_CACHE is not set
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CONFIG_PACKET=m
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# CONFIG_PARTITION_ADVANCED is not set
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CONFIG_PCI=y
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# CONFIG_PCIPCWATCHDOG is not set
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# CONFIG_PCI_DEBUG is not set
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CONFIG_PCI_SYSCALL=y
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# CONFIG_PPP_MPPE is not set
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# CONFIG_PPP_SYNC_TTY is not set
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# CONFIG_PROVE_LOCKING is not set
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# CONFIG_RCU_TORTURE_TEST is not set
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# CONFIG_SCHEDSTATS is not set
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# CONFIG_SCHED_DEBUG is not set
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# CONFIG_SCSI is not set
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# CONFIG_SCSI_DMA is not set
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# CONFIG_SERIAL_8250 is not set
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CONFIG_SERIAL_SL2312=y
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CONFIG_SERIAL_SL2312_CONSOLE=y
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# CONFIG_SL2312_LPC is not set
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# CONFIG_SL2312_MPAGE is not set
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# CONFIG_SL2312_RECVFILE is not set
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# CONFIG_SL2312_SHARE_PIN is not set
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# CONFIG_SL2312_TSO is not set
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# CONFIG_SL2312_USB is not set
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CONFIG_SL3516_ASIC=y
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# CONFIG_SMC91X is not set
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# CONFIG_SOUND is not set
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CONFIG_SPLIT_PTLOCK_CPUS=4096
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# CONFIG_STANDALONE is not set
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CONFIG_SYSFS_DEPRECATED=y
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# CONFIG_SYSVIPC is not set
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CONFIG_SYS_SUPPORTS_APM_EMULATION=y
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# CONFIG_TICK_ONESHOT is not set
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# CONFIG_TIMER_STATS is not set
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# CONFIG_UDF_FS is not set
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CONFIG_UID16=y
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# CONFIG_USB_SUPPORT is not set
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# CONFIG_USER_NS is not set
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CONFIG_VECTORS_BASE=0xffff0000
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# CONFIG_VFAT_FS is not set
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# CONFIG_VGASTATE is not set
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# CONFIG_VIDEO_DEV is not set
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CONFIG_VLAN_8021Q=m
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# CONFIG_W1 is not set
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CONFIG_WATCHDOG_SL351X=y
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# CONFIG_WLAN_80211 is not set
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# CONFIG_XFRM_USER is not set
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# CONFIG_XFS_FS is not set
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# CONFIG_XIP_KERNEL is not set
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_ZBOOT_ROM_TEXT=0x0
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@ -1,46 +0,0 @@
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#
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# Copyright (C) 2007-2008 OpenWrt.org
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#
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# This is free software, licensed under the GNU General Public License v2.
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# See /LICENSE for more information.
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#
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/image.mk
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define Image/Prepare
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cp $(LINUX_DIR)/arch/arm/boot/zImage $(KDIR)/zImage
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endef
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define Image/BuildKernel
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cp $(KDIR)/zImage $(BIN_DIR)/openwrt-$(BOARD)-zImage
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#
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# XXX - FIXME
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#
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# BIN_DIR=$(BIN_DIR) $(TOPDIR)/scripts/arm-magic.sh
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endef
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define Image/Build/jffs2-64k
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dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=64k conv=sync
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endef
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define Image/Build/jffs2-128k
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dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-$(1).img bs=128k conv=sync
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endef
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define Image/Build/squashfs
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$(call prepare_generic_squashfs,$(KDIR)/root.squashfs)
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endef
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define Image/Build
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$(call Image/Build/$(1),$(1))
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dd if=$(KDIR)/root.$(1) of=$(BIN_DIR)/openwrt-$(BOARD)-root.$(1) bs=128k conv=sync
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-$(STAGING_DIR_HOST)/bin/mkfwimage2 \
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-m GEOS -f 0x30000000 -z \
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-v WILI-S.WILIBOARD.v5.00.SL3512.OpenWrt.00000.000000.000000 \
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-o $(BIN_DIR)/openwrt-$(BOARD)-wbd-111-$(1).bin \
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-p Kernel:0x020000:0x100000:0:0:$(BIN_DIR)/openwrt-$(BOARD)-zImage \
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-p Ramdisk:0x120000:0x500000:0:0:$(BIN_DIR)/openwrt-$(BOARD)-root.$(1)
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endef
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||||
|
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$(eval $(call BuildImage))
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||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,11 +0,0 @@
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--- a/include/asm-arm/arch-sl2312/sl351x_gmac.h
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+++ b/include/asm-arm/arch-sl2312/sl351x_gmac.h
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@@ -21,7 +21,7 @@
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#undef BIG_ENDIAN
|
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#define BIG_ENDIAN 0
|
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#define GMAC_DEBUG 1
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-#define GMAC_NUM 2
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+#define GMAC_NUM 1
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//#define L2_jumbo_frame 1
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|
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#define _PACKED_ __attribute__ ((aligned(1), packed))
|
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@ -1,81 +0,0 @@
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--- a/drivers/net/sl351x_gmac.c
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+++ b/drivers/net/sl351x_gmac.c
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@@ -68,9 +68,11 @@
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#include <linux/ip.h>
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#endif
|
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|
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+/* Enables NAPI unconditionally */
|
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+#define CONFIG_SL_NAPI 1
|
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+
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// #define SL351x_TEST_WORKAROUND
|
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#ifdef CONFIG_SL351x_NAT
|
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-#define CONFIG_SL_NAPI 1
|
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#endif
|
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#define GMAX_TX_INTR_DISABLED 1
|
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#define DO_HW_CHKSUM 1
|
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@@ -124,12 +126,17 @@ static char _debug_prefetch_buf[_DEBUG_P
|
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*************************************************************/
|
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static int gmac_initialized = 0;
|
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TOE_INFO_T toe_private_data;
|
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-//static int do_again = 0;
|
||||
+static int do_again = 0;
|
||||
spinlock_t gmac_fq_lock;
|
||||
unsigned int FLAG_SWITCH;
|
||||
|
||||
static unsigned int next_tick = 3 * HZ;
|
||||
-static unsigned char eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
|
||||
+static unsigned char eth_mac[CONFIG_MAC_NUM][6]= {
|
||||
+ {0x00,0x11,0x11,0x87,0x87,0x87},
|
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+#if GMAC_NUM != 1
|
||||
+ {0x00,0x22,0x22,0xab,0xab,0xab}
|
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+#endif
|
||||
+};
|
||||
|
||||
#undef CONFIG_SL351x_RXTOE
|
||||
extern NAT_CFG_T nat_cfg;
|
||||
@@ -2443,7 +2450,8 @@ static irqreturn_t toe_gmac_interrupt (i
|
||||
toe = (TOE_INFO_T *)&toe_private_data;
|
||||
// handle NAPI
|
||||
#ifdef CONFIG_SL_NAPI
|
||||
-if (storlink_ctl.pauseoff == 1)
|
||||
+ /* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
|
||||
+if (1)
|
||||
{
|
||||
/* disable GMAC interrupt */
|
||||
//toe_gmac_disable_interrupt(tp->irq);
|
||||
@@ -2530,7 +2538,7 @@ if (storlink_ctl.pauseoff == 1)
|
||||
{
|
||||
if (likely(netif_rx_schedule_prep(dev)))
|
||||
{
|
||||
- unsigned int data32;
|
||||
+ // unsigned int data32;
|
||||
// disable GMAC-0 rx interrupt
|
||||
// class-Q & TOE-Q are implemented in future
|
||||
//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
@@ -2563,7 +2571,7 @@ if (storlink_ctl.pauseoff == 1)
|
||||
{
|
||||
if (likely(netif_rx_schedule_prep(dev)))
|
||||
{
|
||||
- unsigned int data32;
|
||||
+ // unsigned int data32;
|
||||
// disable GMAC-0 rx interrupt
|
||||
// class-Q & TOE-Q are implemented in future
|
||||
//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
@@ -4217,7 +4225,7 @@ static int gmac_rx_poll(struct net_devic
|
||||
GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
|
||||
unsigned int status4;
|
||||
volatile DMA_RWPTR_T fq_rwptr;
|
||||
- int max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
|
||||
+ // int max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
|
||||
//unsigned long rx_old_bytes;
|
||||
struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
|
||||
//unsigned long long rx_time;
|
||||
@@ -4479,7 +4487,7 @@ static int gmac_rx_poll(struct net_devic
|
||||
|
||||
if (rwptr.bits.rptr == rwptr.bits.wptr)
|
||||
{
|
||||
- unsigned int data32;
|
||||
+ // unsigned int data32;
|
||||
//printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr] rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x, rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
|
||||
|
||||
/* Receive descriptor is empty now */
|
||||
@ -1,248 +0,0 @@
|
||||
--- a/drivers/net/sl351x_gmac.c
|
||||
+++ b/drivers/net/sl351x_gmac.c
|
||||
@@ -127,6 +127,7 @@ static char _debug_prefetch_buf[_DEBUG_P
|
||||
static int gmac_initialized = 0;
|
||||
TOE_INFO_T toe_private_data;
|
||||
static int do_again = 0;
|
||||
+static int rx_poll_enabled;
|
||||
spinlock_t gmac_fq_lock;
|
||||
unsigned int FLAG_SWITCH;
|
||||
|
||||
@@ -1065,7 +1066,8 @@ static void toe_init_gmac(struct net_dev
|
||||
tp->intr3_enabled = 0xffffffff;
|
||||
tp->intr4_selected = GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
|
||||
HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
|
||||
- tp->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
|
||||
+ tp->intr4_enabled = GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT| GMAC0_RX_OVERRUN_INT_BIT;
|
||||
+ // GMAC0_TX_PAUSE_OFF_INT_BIT| GMAC0_MIB_INT_BIT;
|
||||
|
||||
data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
|
||||
writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
|
||||
@@ -1115,7 +1117,7 @@ static void toe_init_gmac(struct net_dev
|
||||
tp->intr3_enabled |= 0xffffffff;
|
||||
tp->intr4_selected |= CLASS_RX_FULL_INT_BITS |
|
||||
HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
|
||||
- tp->intr4_enabled |= SWFQ_EMPTY_INT_BIT;
|
||||
+ tp->intr4_enabled |= SWFQ_EMPTY_INT_BIT | GMAC1_RX_OVERRUN_INT_BIT;
|
||||
}
|
||||
data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) | tp->intr0_selected;
|
||||
writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
|
||||
@@ -2408,7 +2410,7 @@ static inline void toe_gmac_fill_free_q(
|
||||
// unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
|
||||
|
||||
fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
|
||||
- spin_lock_irqsave(&gmac_fq_lock, flags);
|
||||
+ // spin_lock_irqsave(&gmac_fq_lock, flags);
|
||||
//while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
|
||||
// TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
|
||||
while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
|
||||
@@ -2428,10 +2430,47 @@ static inline void toe_gmac_fill_free_q(
|
||||
SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
|
||||
toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
|
||||
}
|
||||
- spin_unlock_irqrestore(&gmac_fq_lock, flags);
|
||||
+ // spin_unlock_irqrestore(&gmac_fq_lock, flags);
|
||||
}
|
||||
// EXPORT_SYMBOL(toe_gmac_fill_free_q);
|
||||
|
||||
+static void gmac_registers(const char *message)
|
||||
+{
|
||||
+ unsigned int status0;
|
||||
+ unsigned int status1;
|
||||
+ unsigned int status2;
|
||||
+ unsigned int status3;
|
||||
+ unsigned int status4;
|
||||
+
|
||||
+ printk("%s\n", message);
|
||||
+
|
||||
+ status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
|
||||
+ status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
|
||||
+ status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
|
||||
+ status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
|
||||
+ status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
|
||||
+
|
||||
+ printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
|
||||
+ status0, status1, status2, status3, status4);
|
||||
+
|
||||
+ status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_0_REG);
|
||||
+ status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
+ status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_2_REG);
|
||||
+ status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_3_REG);
|
||||
+ status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
|
||||
+
|
||||
+ printk("mask : s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
|
||||
+ status0, status1, status2, status3, status4);
|
||||
+
|
||||
+ status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
|
||||
+ status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
|
||||
+ status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
|
||||
+ status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
|
||||
+ status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
|
||||
+
|
||||
+ printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
|
||||
+ status0, status1, status2, status3, status4);
|
||||
+}
|
||||
/*----------------------------------------------------------------------
|
||||
* toe_gmac_interrupt
|
||||
*----------------------------------------------------------------------*/
|
||||
@@ -2492,6 +2531,7 @@ if (1)
|
||||
writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
|
||||
if (status4)
|
||||
writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
|
||||
+
|
||||
#if 0
|
||||
/* handle freeq interrupt first */
|
||||
if (status4 & tp->intr4_enabled) {
|
||||
@@ -2536,10 +2576,31 @@ if (1)
|
||||
}
|
||||
if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
|
||||
{
|
||||
- if (likely(netif_rx_schedule_prep(dev)))
|
||||
+ if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
|
||||
{
|
||||
- // unsigned int data32;
|
||||
- // disable GMAC-0 rx interrupt
|
||||
+ unsigned int data32;
|
||||
+
|
||||
+ if (rx_poll_enabled)
|
||||
+ gmac_registers("check #1");
|
||||
+
|
||||
+ BUG_ON(rx_poll_enabled == 1);
|
||||
+
|
||||
+#if 0
|
||||
+ /* Masks GMAC-0 rx interrupt */
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
+ data32 &= ~(DEFAULT_Q0_INT_BIT);
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
+
|
||||
+ /* Masks GMAC-0 queue empty interrupt */
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
|
||||
+ data32 &= ~DEFAULT_Q0_INT_BIT;
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
|
||||
+
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
|
||||
+ data32 &= ~DEFAULT_Q0_INT_BIT;
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
|
||||
+#endif
|
||||
+
|
||||
// class-Q & TOE-Q are implemented in future
|
||||
//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
//data32 &= ~DEFAULT_Q0_INT_BIT;
|
||||
@@ -2549,7 +2610,8 @@ if (1)
|
||||
//tp->total_q_cnt_napi=0;
|
||||
//rx_time = jiffies;
|
||||
//rx_old_bytes = isPtr->rx_bytes;
|
||||
- __netif_rx_schedule(dev);
|
||||
+ __netif_rx_schedule(dev);
|
||||
+ rx_poll_enabled = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -2569,9 +2631,31 @@ if (1)
|
||||
|
||||
if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
|
||||
{
|
||||
- if (likely(netif_rx_schedule_prep(dev)))
|
||||
+ if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
|
||||
{
|
||||
- // unsigned int data32;
|
||||
+ unsigned int data32;
|
||||
+
|
||||
+ if (rx_poll_enabled)
|
||||
+ gmac_registers("check #2");
|
||||
+
|
||||
+ BUG_ON(rx_poll_enabled == 1);
|
||||
+
|
||||
+#if 0
|
||||
+ /* Masks GMAC-1 rx interrupt */
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
+ data32 &= ~(DEFAULT_Q1_INT_BIT);
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
+
|
||||
+ /* Masks GMAC-1 queue empty interrupt */
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
|
||||
+ data32 &= ~DEFAULT_Q1_INT_BIT;
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
|
||||
+
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
|
||||
+ data32 &= ~DEFAULT_Q1_INT_BIT;
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
|
||||
+#endif
|
||||
+
|
||||
// disable GMAC-0 rx interrupt
|
||||
// class-Q & TOE-Q are implemented in future
|
||||
//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
@@ -2583,9 +2667,13 @@ if (1)
|
||||
//rx_time = jiffies;
|
||||
//rx_old_bytes = isPtr->rx_bytes;
|
||||
__netif_rx_schedule(dev);
|
||||
+ rx_poll_enabled = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
+ } else {
|
||||
+
|
||||
+ gmac_registers("check #3");
|
||||
}
|
||||
|
||||
// Interrupt Status 0
|
||||
@@ -3306,8 +3394,10 @@ next_rx:
|
||||
SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
|
||||
tp->rx_rwptr.bits32 = rwptr.bits32;
|
||||
|
||||
- toe_gmac_fill_free_q();
|
||||
}
|
||||
+
|
||||
+ /* Handles first available packets only then refill the queue. */
|
||||
+ toe_gmac_fill_free_q();
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
@@ -4217,6 +4307,7 @@ static int gmac_rx_poll(struct net_devic
|
||||
GMAC_RXDESC_T *curr_desc;
|
||||
struct sk_buff *skb;
|
||||
DMA_RWPTR_T rwptr;
|
||||
+ unsigned int data32;
|
||||
unsigned int pkt_size;
|
||||
unsigned int desc_count;
|
||||
unsigned int good_frame, chksum_status, rx_status;
|
||||
@@ -4231,7 +4322,7 @@ static int gmac_rx_poll(struct net_devic
|
||||
//unsigned long long rx_time;
|
||||
|
||||
|
||||
-
|
||||
+ BUG_ON(rx_poll_enabled == 0);
|
||||
#if 1
|
||||
if (do_again)
|
||||
{
|
||||
@@ -4516,6 +4607,30 @@ static int gmac_rx_poll(struct net_devic
|
||||
#endif
|
||||
//toe_gmac_fill_free_q();
|
||||
netif_rx_complete(dev);
|
||||
+
|
||||
+ rx_poll_enabled = 0;
|
||||
+
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
+ if (tp->port_id == 0)
|
||||
+ data32 |= DEFAULT_Q0_INT_BIT;
|
||||
+ else
|
||||
+ data32 |= DEFAULT_Q1_INT_BIT;
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
+
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
|
||||
+ if (tp->port_id == 0)
|
||||
+ data32 |= DEFAULT_Q0_INT_BIT;
|
||||
+ else
|
||||
+ data32 |= DEFAULT_Q1_INT_BIT;
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
|
||||
+
|
||||
+ data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
|
||||
+ if (tp->port_id == 0)
|
||||
+ data32 |= DEFAULT_Q0_INT_BIT;
|
||||
+ else
|
||||
+ data32 |= DEFAULT_Q1_INT_BIT;
|
||||
+ writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
|
||||
+
|
||||
// enable GMAC-0 rx interrupt
|
||||
// class-Q & TOE-Q are implemented in future
|
||||
//data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,398 +0,0 @@
|
||||
--- a/arch/arm/mach-sl2312/sl3516_device.c
|
||||
+++ b/arch/arm/mach-sl2312/sl3516_device.c
|
||||
@@ -76,9 +76,30 @@ static struct platform_device sata0_devi
|
||||
.resource = sl3516_sata0_resources,
|
||||
};
|
||||
|
||||
+static struct resource sl351x_wdt_resources[] = {
|
||||
+ [0] = {
|
||||
+ .start = SL2312_WAQTCHDOG_BASE + 0x00,
|
||||
+ .end = SL2312_WAQTCHDOG_BASE + 0x1C,
|
||||
+ .flags = IORESOURCE_MEM,
|
||||
+ },
|
||||
+ [1] = {
|
||||
+ .start = IRQ_WATCHDOG,
|
||||
+ .end = IRQ_WATCHDOG,
|
||||
+ .flags = IORESOURCE_IRQ,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static struct platform_device sl351x_wdt = {
|
||||
+ .name = "sl351x-wdt",
|
||||
+ .id = -1,
|
||||
+ .resource = sl351x_wdt_resources,
|
||||
+ .num_resources = ARRAY_SIZE(sl351x_wdt_resources),
|
||||
+};
|
||||
+
|
||||
static struct platform_device *sata_devices[] __initdata = {
|
||||
&sata_device,
|
||||
&sata0_device,
|
||||
+ &sl351x_wdt,
|
||||
};
|
||||
|
||||
static int __init sl3516_init(void)
|
||||
--- a/drivers/char/watchdog/Kconfig
|
||||
+++ b/drivers/char/watchdog/Kconfig
|
||||
@@ -171,6 +171,17 @@ config EP93XX_WATCHDOG
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called ep93xx_wdt.
|
||||
|
||||
+config WATCHDOG_SL351X
|
||||
+ tristate "SL351x Watchdog"
|
||||
+ depends on WATCHDOG && ARCH_SL2312
|
||||
+ help
|
||||
+ This driver adds watchdog support for the integrated watchdog in the
|
||||
+ SL351x processors (Farraday core). If you have one of these processors
|
||||
+ and wish to have watchdog support enabled, say Y, otherwise say N.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the
|
||||
+ module will be called sl351x_wdt.
|
||||
+
|
||||
config OMAP_WATCHDOG
|
||||
tristate "OMAP Watchdog"
|
||||
depends on ARCH_OMAP16XX || ARCH_OMAP24XX
|
||||
--- a/drivers/char/watchdog/Makefile
|
||||
+++ b/drivers/char/watchdog/Makefile
|
||||
@@ -36,6 +36,7 @@ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c241
|
||||
obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o
|
||||
obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o
|
||||
obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o
|
||||
+obj-$(CONFIG_WATCHDOG_SL351X) += sl351x_wdt.o
|
||||
obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
|
||||
obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
|
||||
obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/char/watchdog/sl351x_wdt.c
|
||||
@@ -0,0 +1,332 @@
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/types.h>
|
||||
+#include <linux/fs.h>
|
||||
+#include <linux/mm.h>
|
||||
+#include <linux/errno.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/miscdevice.h>
|
||||
+#include <linux/watchdog.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <asm/uaccess.h>
|
||||
+#include <asm/arch/sl2312.h>
|
||||
+#include <asm/arch/hardware.h>
|
||||
+#include <asm/arch/irqs.h>
|
||||
+#include <asm/arch/watchdog.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <linux/interrupt.h>
|
||||
+
|
||||
+#define WATCHDOG_TEST 1
|
||||
+#define PFX "sl351x-wdt: "
|
||||
+
|
||||
+#define _WATCHDOG_COUNTER 0x00
|
||||
+#define _WATCHDOG_LOAD 0x04
|
||||
+#define _WATCHDOG_RESTART 0x08
|
||||
+#define _WATCHDOG_CR 0x0C
|
||||
+#define _WATCHDOG_STATUS 0x10
|
||||
+#define _WATCHDOG_CLEAR 0x14
|
||||
+#define _WATCHDOG_INTRLEN 0x18
|
||||
+
|
||||
+static struct resource *wdt_mem;
|
||||
+static struct resource *wdt_irq;
|
||||
+static void __iomem *wdt_base;
|
||||
+static int wdt_margin = WATCHDOG_TIMEOUT_MARGIN; /* in range of 0 .. 60s */
|
||||
+
|
||||
+static int open_state = WATCHDOG_DRIVER_CLOSE;
|
||||
+static int wd_expire = 0;
|
||||
+
|
||||
+static void watchdog_enable(void)
|
||||
+{
|
||||
+ unsigned long wdcr;
|
||||
+
|
||||
+ wdcr = readl(wdt_base + _WATCHDOG_CR);
|
||||
+ wdcr |= (WATCHDOG_WDENABLE_MSK|WATCHDOG_WDRST_MSK);
|
||||
+#ifdef WATCHDOG_TEST
|
||||
+ wdcr |= WATCHDOG_WDINTR_MSK;
|
||||
+// wdcr &= ~WATCHDOG_WDRST_MSK;
|
||||
+#endif
|
||||
+ wdcr &= ~WATCHDOG_WDCLOCK_MSK;
|
||||
+ writel(wdcr, wdt_base + _WATCHDOG_CR);
|
||||
+}
|
||||
+
|
||||
+static void watchdog_set_timeout(unsigned long timeout)
|
||||
+{
|
||||
+ timeout = WATCHDOG_TIMEOUT_SCALE * timeout;
|
||||
+ writel(timeout, wdt_base + _WATCHDOG_LOAD);
|
||||
+ writel(WATCHDOG_RESTART_VALUE, wdt_base + _WATCHDOG_RESTART);
|
||||
+}
|
||||
+
|
||||
+static void watchdog_keepalive(void)
|
||||
+{
|
||||
+ writel(WATCHDOG_RESTART_VALUE, wdt_base + _WATCHDOG_RESTART);
|
||||
+}
|
||||
+
|
||||
+static void watchdog_disable(void)
|
||||
+{
|
||||
+ unsigned long wdcr;
|
||||
+
|
||||
+ wdcr = readl(wdt_base + _WATCHDOG_CR);
|
||||
+ wdcr &= ~WATCHDOG_WDENABLE_MSK;
|
||||
+ writel(wdcr, wdt_base + _WATCHDOG_CR);
|
||||
+}
|
||||
+
|
||||
+
|
||||
+#ifdef WATCHDOG_TEST
|
||||
+static irqreturn_t watchdog_irq(int irq, void *dev_id, struct pt_regs *regs)
|
||||
+{
|
||||
+ unsigned int clear;
|
||||
+
|
||||
+ writel(WATCHDOG_CLEAR_STATUS, wdt_base + _WATCHDOG_CLEAR);
|
||||
+ printk(KERN_INFO PFX "Watchdog timeout, resetting system...\n");
|
||||
+
|
||||
+ clear = __raw_readl(IO_ADDRESS(SL2312_INTERRUPT_BASE)+0x0C);
|
||||
+ clear &= 0x01;
|
||||
+ __raw_writel(clear,IO_ADDRESS(SL2312_INTERRUPT_BASE)+0x08);
|
||||
+ wd_expire = 1;
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
+#endif
|
||||
+
|
||||
+#define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE
|
||||
+static struct watchdog_info sl351x_wdt_ident = {
|
||||
+ .options = OPTIONS,
|
||||
+ .firmware_version = 0,
|
||||
+ .identity = "sl351x Watchdog",
|
||||
+};
|
||||
+
|
||||
+struct file_operations watchdog_fops = {
|
||||
+ .write = watchdog_write,
|
||||
+ .read = watchdog_read,
|
||||
+ .open = watchdog_open,
|
||||
+ .release = watchdog_release,
|
||||
+ .ioctl = watchdog_ioctl,
|
||||
+};
|
||||
+
|
||||
+static int watchdog_open(struct inode *inode, struct file *filp)
|
||||
+{
|
||||
+ if (open_state == WATCHDOG_DRIVER_OPEN)
|
||||
+ return -EBUSY;
|
||||
+
|
||||
+ wd_expire = 0;
|
||||
+
|
||||
+ watchdog_disable();
|
||||
+ watchdog_set_timeout(wdt_margin);
|
||||
+ watchdog_enable();
|
||||
+
|
||||
+ printk(KERN_INFO PFX "watchog timer enabled, margin: %ds.\n", wdt_margin);
|
||||
+ open_state = WATCHDOG_DRIVER_OPEN;
|
||||
+
|
||||
+ return nonseekable_open(inode, filp);
|
||||
+}
|
||||
+
|
||||
+static int watchdog_release(struct inode *inode, struct file *filp)
|
||||
+{
|
||||
+ watchdog_disable();
|
||||
+
|
||||
+ open_state = WATCHDOG_DRIVER_CLOSE;
|
||||
+ wd_expire = 0;
|
||||
+ printk(KERN_INFO PFX "watchog timer disabled, margin: %ds.\n", wdt_margin);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static ssize_t watchdog_read(struct file *filp, char *buf, size_t count, loff_t *off)
|
||||
+{
|
||||
+ int i;
|
||||
+ unsigned long val;
|
||||
+
|
||||
+
|
||||
+ for(i=0;i< count;i++)
|
||||
+ {
|
||||
+ if ((i%4)==0)
|
||||
+ val = *((unsigned long *)WATCHDOG_COUNTER);
|
||||
+ buf[i] = (val & 0xFF);
|
||||
+ val >>= 8;
|
||||
+ }
|
||||
+ return count;
|
||||
+}
|
||||
+
|
||||
+static ssize_t watchdog_write(struct file *filp, const char *buf, size_t len, loff_t *off)
|
||||
+{
|
||||
+ /* Refresh the timer. */
|
||||
+ if (len) {
|
||||
+ watchdog_keepalive();
|
||||
+ }
|
||||
+ return len;
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static int watchdog_ioctl(struct inode *inode, struct file *filp,
|
||||
+ unsigned int cmd, unsigned long arg)
|
||||
+{
|
||||
+ void __user *argp = (void __user *)arg;
|
||||
+ int margin;
|
||||
+
|
||||
+ switch(cmd)
|
||||
+ {
|
||||
+ case WDIOC_GETSUPPORT:
|
||||
+ return copy_to_user(argp, &sl351x_wdt_ident,
|
||||
+ sizeof(sl351x_wdt_ident)) ? -EFAULT : 0;
|
||||
+
|
||||
+ case WDIOC_GETSTATUS:
|
||||
+ case WDIOC_GETBOOTSTATUS:
|
||||
+ return put_user(0, (int __user*)argp);
|
||||
+
|
||||
+ case WDIOC_KEEPALIVE:
|
||||
+ watchdog_keepalive();
|
||||
+ return 0;
|
||||
+
|
||||
+ case WDIOC_SETTIMEOUT:
|
||||
+ if (get_user(margin, (int __user*)argp))
|
||||
+ return -EFAULT;
|
||||
+
|
||||
+ /* Arbitrary, can't find the card's limits */
|
||||
+ if ((margin < 0) || (margin > 60))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ // watchdog_disable();
|
||||
+ wdt_margin = margin;
|
||||
+ watchdog_set_timeout(margin);
|
||||
+ watchdog_keepalive();
|
||||
+ // watchdog_enable();
|
||||
+
|
||||
+ /* Fall through */
|
||||
+
|
||||
+ case WDIOC_GETTIMEOUT:
|
||||
+ return put_user(wdt_margin, (int *)arg);
|
||||
+
|
||||
+ default:
|
||||
+ return -ENOIOCTLCMD;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static struct miscdevice wd_dev= {
|
||||
+ WATCHDOG_MINOR,
|
||||
+ "watchdog",
|
||||
+ &watchdog_fops
|
||||
+};
|
||||
+
|
||||
+static char banner[] __initdata = KERN_INFO "SL351x Watchdog Timer, (c) 2007 WILIBOX\n";
|
||||
+
|
||||
+static int sl351x_wdt_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct resource *res;
|
||||
+ int ret, size;
|
||||
+ unsigned long wdcr;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ if (res == NULL) {
|
||||
+ printk(KERN_INFO PFX "failed to get memory region resouce\n");
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+
|
||||
+ size = (res->end-res->start)+1;
|
||||
+
|
||||
+ wdt_mem = request_mem_region(res->start, size, pdev->name);
|
||||
+ if (wdt_mem == NULL) {
|
||||
+ printk(KERN_INFO PFX "failed to get memory region\n");
|
||||
+ return -ENOENT;
|
||||
+ }
|
||||
+
|
||||
+ wdt_base = ioremap(res->start, size);
|
||||
+ if (wdt_base == NULL) {
|
||||
+ printk(KERN_INFO PFX "failed to ioremap() region\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
+ if (res == NULL) {
|
||||
+ printk(KERN_INFO PFX "failed to get irq resource\n");
|
||||
+ return -ENOENT;
|
||||
+ }
|
||||
+
|
||||
+ wdt_irq = res;
|
||||
+
|
||||
+ ret = request_irq(res->start, watchdog_irq, 0, pdev->name, pdev);
|
||||
+ if (ret != 0) {
|
||||
+ printk(KERN_INFO PFX "failed to install irq (%d)\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ wdcr = readl(wdt_base + _WATCHDOG_CR);
|
||||
+ if (wdcr & WATCHDOG_WDENABLE_MSK) {
|
||||
+ printk(KERN_INFO PFX "Found watchdog in enabled state, reseting ...\n");
|
||||
+ wdcr &= ~WATCHDOG_WDENABLE_MSK;
|
||||
+ writel(wdcr, wdt_base + _WATCHDOG_CR);
|
||||
+ }
|
||||
+
|
||||
+ ret = misc_register(&wd_dev);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int sl351x_wdt_remove(struct platform_device *pdev)
|
||||
+{
|
||||
+ if (wdt_base != NULL) {
|
||||
+ iounmap(wdt_base);
|
||||
+ wdt_base = NULL;
|
||||
+ }
|
||||
+
|
||||
+ if (wdt_irq != NULL) {
|
||||
+ free_irq(wdt_irq->start, pdev);
|
||||
+ release_resource(wdt_irq);
|
||||
+ wdt_irq = NULL;
|
||||
+ }
|
||||
+
|
||||
+ if (wdt_mem != NULL) {
|
||||
+ release_resource(wdt_mem);
|
||||
+ wdt_mem = NULL;
|
||||
+ }
|
||||
+
|
||||
+ misc_deregister(&wd_dev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void sl351x_wdt_shutdown(struct platform_device *dev)
|
||||
+{
|
||||
+ watchdog_disable();
|
||||
+}
|
||||
+
|
||||
+#ifdef CONFIG_PM
|
||||
+static int sl351x_wdt_suspend(struct platform_device *dev, pm_message_t state)
|
||||
+{
|
||||
+ watchdog_disable();
|
||||
+}
|
||||
+
|
||||
+static int sl351x_wdt_resume(struct platform_device *dev)
|
||||
+{
|
||||
+ watchdog_set_timeout(wdt_margin);
|
||||
+ watchdog_enable();
|
||||
+}
|
||||
+
|
||||
+#else
|
||||
+#define sl351x_wdt_suspend NULL
|
||||
+#define sl351x_wdt_resume NULL
|
||||
+#endif
|
||||
+
|
||||
+static struct platform_driver sl351x_wdt_driver = {
|
||||
+ .probe = sl351x_wdt_probe,
|
||||
+ .remove = sl351x_wdt_remove,
|
||||
+ .shutdown = sl351x_wdt_shutdown,
|
||||
+ .suspend = sl351x_wdt_suspend,
|
||||
+ .resume = sl351x_wdt_resume,
|
||||
+ .driver = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .name = "sl351x-wdt",
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static int __init watchdog_init(void)
|
||||
+{
|
||||
+ printk(banner);
|
||||
+ return platform_driver_register(&sl351x_wdt_driver);
|
||||
+}
|
||||
+
|
||||
+static void __exit watchdog_exit(void)
|
||||
+{
|
||||
+ platform_driver_unregister(&sl351x_wdt_driver);
|
||||
+}
|
||||
+
|
||||
+module_init(watchdog_init);
|
||||
+module_exit(watchdog_exit);
|
||||
@ -1,384 +0,0 @@
|
||||
--- /dev/null
|
||||
+++ b/drivers/char/gemini_gpio_dev.c
|
||||
@@ -0,0 +1,356 @@
|
||||
+/*
|
||||
+ * GPIO driver for Gemini board
|
||||
+ * Provides /dev/gpio
|
||||
+ */
|
||||
+
|
||||
+#include <linux/version.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/init.h>
|
||||
+#include <linux/proc_fs.h>
|
||||
+#include <linux/fcntl.h>
|
||||
+#include <linux/miscdevice.h>
|
||||
+#include <asm/uaccess.h> /* copy_to_user, copy_from_user */
|
||||
+
|
||||
+#include <asm/hardware.h>
|
||||
+#include <asm/io.h>
|
||||
+#include <asm/arch/sl2312.h>
|
||||
+#include <asm/arch/irqs.h>
|
||||
+#include <asm/arch/gemini_gpio.h>
|
||||
+
|
||||
+#define GEMINI_GPIO_BASE1 IO_ADDRESS(SL2312_GPIO_BASE)
|
||||
+#define GEMINI_GPIO_BASE2 IO_ADDRESS(SL2312_GPIO_BASE1)
|
||||
+
|
||||
+#define GPIO_SET 2
|
||||
+#define MAX_GPIO_LINE 32*GPIO_SET
|
||||
+
|
||||
+wait_queue_head_t gemini_gpio_wait[MAX_GPIO_LINE];
|
||||
+
|
||||
+enum GPIO_REG
|
||||
+{
|
||||
+ GPIO_DATA_OUT = 0x00,
|
||||
+ GPIO_DATA_IN = 0x04,
|
||||
+ GPIO_PIN_DIR = 0x08,
|
||||
+ GPIO_BY_PASS = 0x0C,
|
||||
+ GPIO_DATA_SET = 0x10,
|
||||
+ GPIO_DATA_CLEAR = 0x14,
|
||||
+ GPIO_PULL_ENABLE = 0x18,
|
||||
+ GPIO_PULL_TYPE = 0x1C,
|
||||
+ GPIO_INT_ENABLE = 0x20,
|
||||
+ GPIO_INT_RAW_STATUS = 0x24,
|
||||
+ GPIO_INT_MASK_STATUS = 0x28,
|
||||
+ GPIO_INT_MASK = 0x2C,
|
||||
+ GPIO_INT_CLEAR = 0x30,
|
||||
+ GPIO_INT_TRIG = 0x34,
|
||||
+ GPIO_INT_BOTH = 0x38,
|
||||
+ GPIO_INT_POLAR = 0x3C
|
||||
+};
|
||||
+
|
||||
+unsigned int regist_gpio_int0=0,regist_gpio_int1=0;
|
||||
+
|
||||
+/* defines a specific GPIO bit number and state */
|
||||
+struct gpio_bit {
|
||||
+ unsigned char bit;
|
||||
+ unsigned char state;
|
||||
+};
|
||||
+
|
||||
+#define GPIO_MAJOR 10
|
||||
+#define GPIO_MINOR 127
|
||||
+
|
||||
+/*
|
||||
+ * ioctl calls that are permitted to the /dev/gpio interface
|
||||
+ */
|
||||
+#define GPIO_GET_BIT 0x0000001
|
||||
+#define GPIO_SET_BIT 0x0000002
|
||||
+#define GPIO_GET_CONFIG 0x0000003
|
||||
+#define GPIO_SET_CONFIG 0x0000004
|
||||
+
|
||||
+//#define GPIO_CONFIG_OUT 1
|
||||
+//#define GPIO_CONFIG_IN 2
|
||||
+
|
||||
+
|
||||
+
|
||||
+#define DEVICE_NAME "gpio"
|
||||
+
|
||||
+//#define DEBUG
|
||||
+
|
||||
+/*
|
||||
+ * GPIO interface
|
||||
+ */
|
||||
+
|
||||
+/* /dev/gpio */
|
||||
+static int gpio_ioctl(struct inode *inode, struct file *file,
|
||||
+ unsigned int cmd, unsigned long arg);
|
||||
+
|
||||
+/* /proc/driver/gpio */
|
||||
+static int gpio_read_proc(char *page, char **start, off_t off,
|
||||
+ int count, int *eof, void *data);
|
||||
+
|
||||
+static unsigned char gpio_status; /* bitmapped status byte. */
|
||||
+
|
||||
+/* functions for set/get gpio lines on storlink cpu */
|
||||
+
|
||||
+void gpio_line_get(unsigned char pin, u32 * data)
|
||||
+{
|
||||
+ unsigned int set = pin >>5; // each GPIO set has 32 pins
|
||||
+ unsigned int status,addr;
|
||||
+
|
||||
+ addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1) + GPIO_DATA_IN;
|
||||
+ status = readl(addr);
|
||||
+#ifdef DEBUG
|
||||
+ printk("status = %08X, pin = %d, set = %d\n", status, pin, set);
|
||||
+#endif
|
||||
+ if (set)
|
||||
+ *data = (status&(1<<(pin-32)))?1:0;
|
||||
+ else
|
||||
+ *data = (status&(1<<pin))?1:0;
|
||||
+}
|
||||
+
|
||||
+void gpio_line_set(unsigned char pin, u32 high)
|
||||
+{
|
||||
+ unsigned char set = pin >>5; // each GPIO set has 32 pins
|
||||
+ unsigned int status=0,addr;
|
||||
+
|
||||
+ addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+(high?GPIO_DATA_SET:GPIO_DATA_CLEAR);
|
||||
+
|
||||
+ status &= ~(1 << (pin %32));
|
||||
+ status |= (1 << (pin % 32));
|
||||
+ writel(status,addr);
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * pin = [0..63]
|
||||
+ * mode =
|
||||
+ * 1 -- OUT
|
||||
+ * 2 -- IN
|
||||
+ */
|
||||
+void gpio_line_config(unsigned char pin, unsigned char mode)
|
||||
+{
|
||||
+ unsigned char set = pin >>5; // each GPIO set has 32 pins
|
||||
+ unsigned int status,addr;
|
||||
+
|
||||
+ addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+GPIO_PIN_DIR;
|
||||
+ status = readl(addr);
|
||||
+
|
||||
+ status &= ~(1 << (pin %32));
|
||||
+ if (mode == 1)
|
||||
+ status |= (1 << (pin % 32)); /* PinDir: 0 - input, 1 - output */
|
||||
+
|
||||
+ writel(status,addr);
|
||||
+#if 0
|
||||
+ /* enable pullup-high if mode is input */
|
||||
+
|
||||
+ addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+GPIO_PULL_ENABLE;
|
||||
+ status = readl(addr);
|
||||
+
|
||||
+ status &= ~(1 << (pin %32));
|
||||
+ if (mode == 2) /* input */
|
||||
+ status |= (1 << (pin % 32)); /* PullEnable: 0 - disable, 1 - enable */
|
||||
+
|
||||
+ writel(status,addr);
|
||||
+
|
||||
+ addr = (set ? GEMINI_GPIO_BASE2:GEMINI_GPIO_BASE1)+GPIO_PULL_TYPE;
|
||||
+ status = readl(addr);
|
||||
+
|
||||
+ status &= ~(1 << (pin %32));
|
||||
+ if (mode == 2) /* input */
|
||||
+ status |= (1 << (pin % 32)); /* PullType: 0 - low, 1 - high */
|
||||
+
|
||||
+ writel(status,addr);
|
||||
+#endif
|
||||
+}
|
||||
+
|
||||
+#define GPIO_IS_OPEN 0x01 /* means /dev/gpio is in use */
|
||||
+
|
||||
+/*
|
||||
+ * Now all the various file operations that we export.
|
||||
+ */
|
||||
+static int gpio_ioctl(struct inode *inode, struct file *file,
|
||||
+ unsigned int cmd, unsigned long arg)
|
||||
+{
|
||||
+ struct gpio_bit bit;
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (copy_from_user(&bit, (struct gpio_bit *)arg,
|
||||
+ sizeof(bit)))
|
||||
+ return -EFAULT;
|
||||
+
|
||||
+ switch (cmd) {
|
||||
+
|
||||
+ case GPIO_GET_BIT:
|
||||
+ gpio_line_get(bit.bit, &val);
|
||||
+ bit.state = val;
|
||||
+ return copy_to_user((void *)arg, &bit, sizeof(bit)) ? -EFAULT : 0;
|
||||
+ case GPIO_SET_BIT:
|
||||
+ val = bit.state;
|
||||
+ gpio_line_set(bit.bit, val);
|
||||
+ return 0;
|
||||
+ case GPIO_GET_CONFIG:
|
||||
+ // gpio_line_config(bit.bit, bit.state);
|
||||
+ return copy_to_user((void *)arg, &bit, sizeof(bit)) ? -EFAULT : 0;
|
||||
+ case GPIO_SET_CONFIG:
|
||||
+ val = bit.state;
|
||||
+ gpio_line_config(bit.bit, bit.state);
|
||||
+ return 0;
|
||||
+ }
|
||||
+ return -EINVAL;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+static int gpio_open(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ if (gpio_status & GPIO_IS_OPEN)
|
||||
+ return -EBUSY;
|
||||
+
|
||||
+ gpio_status |= GPIO_IS_OPEN;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+static int gpio_release(struct inode *inode, struct file *file)
|
||||
+{
|
||||
+ /*
|
||||
+ * Turn off all interrupts once the device is no longer
|
||||
+ * in use and clear the data.
|
||||
+ */
|
||||
+
|
||||
+ gpio_status &= ~GPIO_IS_OPEN;
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+/*
|
||||
+ * The various file operations we support.
|
||||
+ */
|
||||
+
|
||||
+static struct file_operations gpio_fops = {
|
||||
+ .owner = THIS_MODULE,
|
||||
+ .ioctl = gpio_ioctl,
|
||||
+ .open = gpio_open,
|
||||
+ .release = gpio_release,
|
||||
+};
|
||||
+
|
||||
+static struct miscdevice gpio_dev =
|
||||
+{
|
||||
+ .minor = GPIO_MINOR,
|
||||
+ .name = "gpio",
|
||||
+ .fops = &gpio_fops,
|
||||
+};
|
||||
+
|
||||
+
|
||||
+
|
||||
+
|
||||
+#ifdef CONFIG_PROC_FS
|
||||
+static struct proc_dir_entry *dir;
|
||||
+
|
||||
+/*
|
||||
+ * Info exported via "/proc/driver/gpio".
|
||||
+ */
|
||||
+static int gpio_get_status(char *buf)
|
||||
+{
|
||||
+ char *p = buf;
|
||||
+ u32 val = 0;
|
||||
+ int i;
|
||||
+ int bit;
|
||||
+#ifdef DEBUG
|
||||
+ u32 addr;
|
||||
+
|
||||
+ for (i = 0; i < 0x20; i+=4 ) {
|
||||
+ addr = IO_ADDRESS(SL2312_GPIO_BASE) + i;
|
||||
+ val = readl(addr);
|
||||
+ p+=sprintf(p, "GPIO0: 0x%02X: %08X\n", i, val );
|
||||
+ }
|
||||
+ for (i = 0; i < 0x20; i+=4 ) {
|
||||
+ addr = IO_ADDRESS(SL2312_GPIO_BASE1) + i;
|
||||
+ val = readl(addr);
|
||||
+ p+=sprintf(p, "GPIO1: 0x%02X: %08X\n", i, val );
|
||||
+ }
|
||||
+#endif
|
||||
+
|
||||
+ for (i = 0; i < 32; i++) {
|
||||
+ gpio_line_get(i, &bit);
|
||||
+ if (bit)
|
||||
+ val |= (1 << i);
|
||||
+ }
|
||||
+ p += sprintf(p, "gpio0\t: 0x%08x\n", val);
|
||||
+
|
||||
+ val = 0;
|
||||
+ for (i = 32; i < 64; i++) {
|
||||
+ gpio_line_get(i, &bit);
|
||||
+ if (bit)
|
||||
+ val |= (1 << i);
|
||||
+ }
|
||||
+ p += sprintf(p, "gpio1\t: 0x%08x\n", val);
|
||||
+
|
||||
+ return p - buf;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+/* /proc/driver/gpio read op
|
||||
+ */
|
||||
+static int gpio_read_proc(char *page, char **start, off_t off,
|
||||
+ int count, int *eof, void *data)
|
||||
+{
|
||||
+ int len = gpio_get_status (page);
|
||||
+
|
||||
+ if (len <= off+count)
|
||||
+ *eof = 1;
|
||||
+ *start = page + off;
|
||||
+ len -= off;
|
||||
+ if ( len > count )
|
||||
+ len = count;
|
||||
+ if ( len < 0 )
|
||||
+ len = 0;
|
||||
+ return len;
|
||||
+}
|
||||
+#endif /* CONFIG_PROC_FS */
|
||||
+
|
||||
+
|
||||
+static int __init gpio_init_module(void)
|
||||
+{
|
||||
+ int retval;
|
||||
+#ifdef CONFIG_PROC_FS
|
||||
+ struct proc_dir_entry *res;
|
||||
+#endif
|
||||
+
|
||||
+ /* register /dev/gpio file ops */
|
||||
+ //retval = register_chrdev(GPIO_MAJOR, DEVICE_NAME, &gpio_fops);
|
||||
+ retval = misc_register(&gpio_dev);
|
||||
+ if(retval < 0)
|
||||
+ return retval;
|
||||
+
|
||||
+#ifdef CONFIG_PROC_FS
|
||||
+ dir = proc_mkdir("driver/gpio", NULL);
|
||||
+ if (!dir) {
|
||||
+ misc_deregister(&gpio_dev);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+ /* register /proc/driver/gpio */
|
||||
+ res = create_proc_entry("info", 0644, dir);
|
||||
+ if (res) {
|
||||
+ res->read_proc= gpio_read_proc;
|
||||
+ } else {
|
||||
+ misc_deregister(&gpio_dev);
|
||||
+ return -ENOMEM;
|
||||
+ }
|
||||
+#endif
|
||||
+
|
||||
+ printk("%s: GPIO driver loaded\n", __FILE__);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void __exit gpio_cleanup_module(void)
|
||||
+{
|
||||
+ remove_proc_entry ("info", dir);
|
||||
+ misc_deregister(&gpio_dev);
|
||||
+
|
||||
+ printk("%s: GPIO driver unloaded\n", __FILE__);
|
||||
+}
|
||||
+
|
||||
+module_init(gpio_init_module);
|
||||
+module_exit(gpio_cleanup_module);
|
||||
+
|
||||
+MODULE_AUTHOR("Jonas Majauskas");
|
||||
+MODULE_LICENSE("GPL");
|
||||
+
|
||||
--- a/drivers/char/Kconfig
|
||||
+++ b/drivers/char/Kconfig
|
||||
@@ -1071,5 +1071,12 @@ config DEVPORT
|
||||
|
||||
source "drivers/s390/char/Kconfig"
|
||||
|
||||
+config GEMINI_GPIO_DEV
|
||||
+ tristate "GPIO driver for Gemini board (provides /dev/gpio)"
|
||||
+ depends on ARCH_SL2312
|
||||
+ default n
|
||||
+ help
|
||||
+ GPIO driver for Gemini boards - SL3512, SL3516.
|
||||
+
|
||||
endmenu
|
||||
|
||||
--- a/drivers/char/Makefile
|
||||
+++ b/drivers/char/Makefile
|
||||
@@ -116,6 +116,7 @@ obj-$(CONFIG_IPMI_HANDLER) += ipmi/
|
||||
|
||||
obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
|
||||
obj-$(CONFIG_TCG_TPM) += tpm/
|
||||
+obj-$(CONFIG_GEMINI_GPIO_DEV) += gemini_gpio_dev.o
|
||||
|
||||
obj-$(CONFIG_PS3_FLASH) += ps3flash.o
|
||||
|
||||
@ -35,7 +35,7 @@ config EABI_SUPPORT
|
||||
bool
|
||||
depends arm||armeb
|
||||
prompt "Enable EABI support" if TOOLCHAINOPTS
|
||||
default n if (TARGET_gemini || TARGET_storm)
|
||||
default n if TARGET_gemini
|
||||
default y
|
||||
help
|
||||
Enable ARM EABI support
|
||||
|
||||
Loading…
Reference in New Issue
Block a user