ar71xx: add kernel support for the OpenMesh OM5P-ACv2 board
Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> SVN-Revision: 49149
This commit is contained in:
John Crispin
parent
0211fa1253
commit
886cb9a744
@ -110,6 +110,7 @@ CONFIG_ATH79_MACH_NBG6716=y
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CONFIG_ATH79_MACH_OM2P=y
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CONFIG_ATH79_MACH_OM5P=y
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CONFIG_ATH79_MACH_OM5P_AC=y
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CONFIG_ATH79_MACH_OM5P_ACv2=y
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CONFIG_ATH79_MACH_OMY_X1=y
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CONFIG_ATH79_MACH_ONION_OMEGA=y
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CONFIG_ATH79_MACH_PB42=y
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@ -113,6 +113,7 @@ CONFIG_ATH79_MACH_NBG6716=y
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CONFIG_ATH79_MACH_OM2P=y
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CONFIG_ATH79_MACH_OM5P=y
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CONFIG_ATH79_MACH_OM5P_AC=y
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CONFIG_ATH79_MACH_OM5P_ACv2=y
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CONFIG_ATH79_MACH_OMY_X1=y
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CONFIG_ATH79_MACH_ONION_OMEGA=y
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CONFIG_ATH79_MACH_PB42=y
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@ -870,6 +870,16 @@ config ATH79_MACH_OM5P_AC
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select ATH79_DEV_M25P80
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select ATH79_DEV_WMAC
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config ATH79_MACH_OM5P_ACv2
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bool "OpenMesh OM5P-ACv2 board support"
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select SOC_QCA955X
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select ATH79_DEV_AP9X_PCI if PCI
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select ATH79_DEV_ETH
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select ATH79_DEV_GPIO_BUTTONS
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_M25P80
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select ATH79_DEV_WMAC
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config ATH79_MACH_OMY_X1
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bool "OMYlink OMY X1 support"
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select SOC_AR934X
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@ -116,6 +116,7 @@ obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o
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obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
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obj-$(CONFIG_ATH79_MACH_OM5P) += mach-om5p.o
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obj-$(CONFIG_ATH79_MACH_OM5P_AC) += mach-om5pac.o
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obj-$(CONFIG_ATH79_MACH_OM5P_ACv2) += mach-om5pacv2.o
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obj-$(CONFIG_ATH79_MACH_OMY_X1) += mach-omy-x1.o
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obj-$(CONFIG_ATH79_MACH_ONION_OMEGA) += mach-onion-omega.o
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obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
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216
target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c
Normal file
216
target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c
Normal file
@ -0,0 +1,216 @@
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/*
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* OpenMesh OM5P-ACv2 support
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*
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* Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
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* Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com>
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* Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/mdio-gpio.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/i2c-gpio.h>
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#include <linux/platform_data/phy-at803x.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#include "pci.h"
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#define OM5PACV2_GPIO_LED_POWER 14
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#define OM5PACV2_GPIO_LED_GREEN 13
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#define OM5PACV2_GPIO_LED_RED 23
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#define OM5PACV2_GPIO_LED_YELLOW 15
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#define OM5PACV2_GPIO_BTN_RESET 1
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#define OM5PACV2_GPIO_I2C_SCL 18
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#define OM5PACV2_GPIO_I2C_SDA 19
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#define OM5PACV2_GPIO_PA_DCDC 2
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#define OM5PACV2_GPIO_PA_HIGH 16
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#define OM5PACV2_KEYS_POLL_INTERVAL 20 /* msecs */
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#define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL)
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#define OM5PACV2_WMAC_CALDATA_OFFSET 0x1000
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static struct gpio_led om5pacv2_leds_gpio[] __initdata = {
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{
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.name = "om5pac:blue:power",
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.gpio = OM5PACV2_GPIO_LED_POWER,
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.active_low = 1,
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}, {
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.name = "om5pac:red:wifi",
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.gpio = OM5PACV2_GPIO_LED_RED,
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.active_low = 1,
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}, {
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.name = "om5pac:yellow:wifi",
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.gpio = OM5PACV2_GPIO_LED_YELLOW,
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.active_low = 1,
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}, {
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.name = "om5pac:green:wifi",
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.gpio = OM5PACV2_GPIO_LED_GREEN,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL,
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.gpio = OM5PACV2_GPIO_BTN_RESET,
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.active_low = 1,
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}
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};
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static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = {
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.sda_pin = OM5PACV2_GPIO_I2C_SDA,
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.scl_pin = OM5PACV2_GPIO_I2C_SCL,
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.udelay = 10,
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.sda_is_open_drain = 1,
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.scl_is_open_drain = 1,
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};
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static struct platform_device om5pacv2_i2c_device = {
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.name = "i2c-gpio",
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.id = 0,
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.dev = {
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.platform_data = &om5pacv2_i2c_device_platdata,
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},
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};
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static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = {
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{
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I2C_BOARD_INFO("tmp423", 0x4e),
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},
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};
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static struct flash_platform_data om5pacv2_flash_data = {
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.type = "mx25l12805d",
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};
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static struct at803x_platform_data om5pacv2_an_at803x_data = {
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.disable_smarteee = 1,
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.enable_rgmii_rx_delay = 1,
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.enable_rgmii_tx_delay = 1,
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};
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static struct at803x_platform_data om5pacv2_an_at8031_data = {
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.disable_smarteee = 1,
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.enable_rgmii_rx_delay = 1,
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.enable_rgmii_tx_delay = 1,
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};
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static struct mdio_board_info om5pacv2_an_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 4,
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.platform_data = &om5pacv2_an_at803x_data,
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},
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{
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.bus_id = "ag71xx-mdio.1",
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.phy_addr = 1,
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.platform_data = &om5pacv2_an_at8031_data,
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},
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};
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static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask,
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unsigned int rxd,
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unsigned int rxdv,
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unsigned int txd,
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unsigned int txe)
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{
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void __iomem *base;
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u32 t;
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base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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t = mask;
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t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
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t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
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t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
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t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
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__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
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iounmap(base);
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}
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static void __init om5p_acv2_setup(void)
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{
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u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
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u8 mac[6];
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/* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
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ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
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ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
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ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
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gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
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"PA DC/DC");
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gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
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/* temperature sensor */
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platform_device_register(&om5pacv2_i2c_device);
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i2c_register_board_info(0, om5pacv2_i2c_devs,
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ARRAY_SIZE(om5pacv2_i2c_devs));
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ath79_register_m25p80(&om5pacv2_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
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om5pacv2_leds_gpio);
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ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(om5pacv2_gpio_keys),
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om5pacv2_gpio_keys);
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ath79_init_mac(mac, art, 0x02);
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ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
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om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
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ath79_register_mdio(0, 0x0);
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ath79_register_mdio(1, 0x0);
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mdiobus_register_board_info(om5pacv2_an_mdio0_info,
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ARRAY_SIZE(om5pacv2_an_mdio0_info));
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ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
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ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
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/* GMAC0 is connected to the PHY4 */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_data.phy_mask = BIT(4);
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ath79_eth0_pll_data.pll_1000 = 0x82000101;
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ath79_eth0_pll_data.pll_100 = 0x80000101;
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ath79_eth0_pll_data.pll_10 = 0x80001313;
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ath79_register_eth(0);
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/* GMAC1 is connected to MDIO1 in SGMII mode */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
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ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_eth1_data.phy_mask = BIT(1);
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ath79_eth1_pll_data.pll_1000 = 0x03000101;
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ath79_eth1_pll_data.pll_100 = 0x80000101;
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ath79_eth1_pll_data.pll_10 = 0x80001313;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_register_eth(1);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup);
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@ -114,6 +114,7 @@ enum ath79_mach_type {
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ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */
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ATH79_MACH_OM2P, /* OpenMesh OM2P */
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ATH79_MACH_OM5P_AC, /* OpenMesh OM5P-AC */
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ATH79_MACH_OM5P_ACv2, /* OpenMesh OM5P-ACv2 */
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ATH79_MACH_OM5P_AN, /* OpenMesh OM5P-AN */
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ATH79_MACH_OM5P, /* OpenMesh OM5P */
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ATH79_MACH_OMY_X1, /* OMYlink OMY-X1 */
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