ar71xx: enable MIB counters in the built-in switch of the AR934x
SVN-Revision: 31476
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@ -83,6 +83,7 @@
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#define AR7240_MIB_AT_HALF_EN BIT(16)
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#define AR7240_MIB_BUSY BIT(17)
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#define AR7240_MIB_FUNC_S 24
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#define AR7240_MIB_FUNC_M BITM(3)
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#define AR7240_MIB_FUNC_NO_OP 0x0
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#define AR7240_MIB_FUNC_FLUSH 0x1
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#define AR7240_MIB_FUNC_CAPTURE 0x3
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@ -218,6 +219,8 @@
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#define AR934X_AT_CTRL_AGE_EN BIT(17)
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#define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
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#define AR934X_MIB_ENABLE BIT(30)
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#define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
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#define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
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@ -517,8 +520,9 @@ static int ar7240sw_capture_stats(struct ar7240sw *as)
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write_lock(&as->stats_lock);
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/* Capture the hardware statistics for all ports */
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ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
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(AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
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ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
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(AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
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(AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
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/* Wait for the capturing to complete. */
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ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
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@ -579,6 +583,11 @@ static void ar7240sw_setup(struct ar7240sw *as)
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/* Enable Broadcast frames transmitted to the CPU */
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ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
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AR934X_FLOOD_MASK_BC_DP(0));
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/* Enable MIB counters */
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ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
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AR934X_MIB_ENABLE);
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} else {
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/* Enable ARP frame acknowledge, aging, MAC replacing */
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ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
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