From ab7087e24f9ea37e126d71de27fae8a3a5af2caf Mon Sep 17 00:00:00 2001 From: Daniel Golle Date: Sat, 11 Mar 2017 14:10:16 +0100 Subject: [PATCH] rt2x00: mt7620: make fixes requested upstream Introduce RT6352 instead of matching against RF7620. Clean up channel setting rfvals. Port bandwidth filter calibration. Signed-off-by: Daniel Golle --- .../621-rt2x00-add-support-for-mt7620.patch | 844 ++++++++++++++---- 1 file changed, 674 insertions(+), 170 deletions(-) diff --git a/package/kernel/mac80211/patches/621-rt2x00-add-support-for-mt7620.patch b/package/kernel/mac80211/patches/621-rt2x00-add-support-for-mt7620.patch index c2ecf0ccc2..b7a0ad1327 100644 --- a/package/kernel/mac80211/patches/621-rt2x00-add-support-for-mt7620.patch +++ b/package/kernel/mac80211/patches/621-rt2x00-add-support-for-mt7620.patch @@ -1,13 +1,28 @@ -From: Roman Yeryomin +From 5a53fd87e4691343fdb60be147ee859975071df6 Mon Sep 17 00:00:00 2001 +In-Reply-To: <20170311103750.GA17556@redhat.com> +References: <20170311103750.GA17556@redhat.com> +From: Daniel Golle Date: Tue, 1 Jul 2014 10:26:18 +0000 -Subject: [PATCH] mac80211: rt2x00: add support for mt7620 +Subject: [PATCH] mac80211: rt2x00: add support for MT7620 +To: Stanislaw Gruszka +Cc: Helmut Schaa , + linux-wireless@vger.kernel.org, + Kalle Valo -Support for MT7620 was added to OpenWrt in r41441 and heavily reworked +From: Roman Yeryomin + +Basic support for MT7620 built-in wireless radio was added to +OpenWrt in r41441. It has seen some heavy cleaning and refactoring since in order to match the Kernel's code quality standards. Signed-off-by: Roman Yeryomin Signed-off-by: Daniel Golle --- + drivers/net/wireless/ralink/rt2x00/rt2800.h | 177 +++ + drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 1421 +++++++++++++++++++++++- + drivers/net/wireless/ralink/rt2x00/rt2800lib.h | 4 + + drivers/net/wireless/ralink/rt2x00/rt2x00.h | 1 + + 4 files changed, 1577 insertions(+), 26 deletions(-) --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h @@ -19,7 +34,7 @@ Signed-off-by: Daniel Golle /* * Chipset revisions. -@@ -641,6 +642,14 @@ +@@ -641,6 +642,24 @@ #define RF_CSR_CFG_BUSY FIELD32(0x00020000) /* @@ -30,11 +45,21 @@ Signed-off-by: Daniel Golle +#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010) +#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001) + ++/* undocumented registers for calibration of new MAC */ ++#define RF_CONTROL0 0x0518 ++#define RF_BYPASS0 0x051c ++#define RF_CONTROL1 0x0520 ++#define RF_BYPASS1 0x0524 ++#define RF_CONTROL2 0x0528 ++#define RF_BYPASS2 0x052c ++#define RF_CONTROL3 0x0530 ++#define RF_BYPASS3 0x0534 ++ +/* * EFUSE_CSR: RT30x0 EEPROM */ #define EFUSE_CTRL 0x0580 -@@ -1024,6 +1033,16 @@ +@@ -1024,6 +1043,16 @@ #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000) /* @@ -51,7 +76,7 @@ Signed-off-by: Daniel Golle * EDCA_AC0_CFG: */ #define EDCA_AC0_CFG 0x1300 -@@ -1097,6 +1116,12 @@ +@@ -1097,6 +1126,12 @@ #define TX_PWR_CFG_0_OFDM6_CH1 FIELD32(0x00f00000) #define TX_PWR_CFG_0_OFDM12_CH0 FIELD32(0x0f000000) #define TX_PWR_CFG_0_OFDM12_CH1 FIELD32(0xf0000000) @@ -64,7 +89,7 @@ Signed-off-by: Daniel Golle /* * TX_PWR_CFG_1: -@@ -1119,6 +1144,11 @@ +@@ -1119,6 +1154,11 @@ #define TX_PWR_CFG_1_MCS0_CH1 FIELD32(0x00f00000) #define TX_PWR_CFG_1_MCS2_CH0 FIELD32(0x0f000000) #define TX_PWR_CFG_1_MCS2_CH1 FIELD32(0xf0000000) @@ -76,7 +101,7 @@ Signed-off-by: Daniel Golle /* * TX_PWR_CFG_2: -@@ -1141,6 +1171,11 @@ +@@ -1141,6 +1181,11 @@ #define TX_PWR_CFG_2_MCS8_CH1 FIELD32(0x00f00000) #define TX_PWR_CFG_2_MCS10_CH0 FIELD32(0x0f000000) #define TX_PWR_CFG_2_MCS10_CH1 FIELD32(0xf0000000) @@ -88,7 +113,7 @@ Signed-off-by: Daniel Golle /* * TX_PWR_CFG_3: -@@ -1163,6 +1198,11 @@ +@@ -1163,6 +1208,11 @@ #define TX_PWR_CFG_3_STBC0_CH1 FIELD32(0x00f00000) #define TX_PWR_CFG_3_STBC2_CH0 FIELD32(0x0f000000) #define TX_PWR_CFG_3_STBC2_CH1 FIELD32(0xf0000000) @@ -100,18 +125,17 @@ Signed-off-by: Daniel Golle /* * TX_PWR_CFG_4: -@@ -1177,6 +1217,10 @@ +@@ -1177,6 +1227,9 @@ #define TX_PWR_CFG_3_STBC4_CH1 FIELD32(0x000000f0) #define TX_PWR_CFG_3_STBC6_CH0 FIELD32(0x00000f00) #define TX_PWR_CFG_3_STBC6_CH1 FIELD32(0x0000f000) +/* bits for new 2T devices */ +#define TX_PWR_CFG_4B_STBC_MCS4_MCS5 FIELD32(0x000000ff) +#define TX_PWR_CFG_4B_STBC_MCS6 FIELD32(0x0000ff00) -+ /* * TX_PIN_CFG: -@@ -1203,6 +1247,8 @@ +@@ -1203,6 +1256,8 @@ #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000) #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000) #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000) @@ -120,7 +144,7 @@ Signed-off-by: Daniel Golle #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000) #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000) #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000) -@@ -1549,6 +1595,95 @@ +@@ -1549,6 +1604,95 @@ #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f) #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00) @@ -216,7 +240,7 @@ Signed-off-by: Daniel Golle /* TX_PWR_CFG_7 */ #define TX_PWR_CFG_7 0x13d4 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f) -@@ -1557,6 +1692,10 @@ +@@ -1557,6 +1701,10 @@ #define TX_PWR_CFG_7_MCS7_CH0 FIELD32(0x000f0000) #define TX_PWR_CFG_7_MCS7_CH1 FIELD32(0x00f00000) #define TX_PWR_CFG_7_MCS7_CH2 FIELD32(0x0f000000) @@ -227,7 +251,7 @@ Signed-off-by: Daniel Golle /* TX_PWR_CFG_8 */ #define TX_PWR_CFG_8 0x13d8 -@@ -1566,12 +1705,17 @@ +@@ -1566,12 +1714,17 @@ #define TX_PWR_CFG_8_MCS23_CH0 FIELD32(0x000f0000) #define TX_PWR_CFG_8_MCS23_CH1 FIELD32(0x00f00000) #define TX_PWR_CFG_8_MCS23_CH2 FIELD32(0x0f000000) @@ -245,7 +269,23 @@ Signed-off-by: Daniel Golle /* * TX_TXBF_CFG: -@@ -2175,6 +2319,12 @@ struct mac_iveiv_entry { +@@ -2151,12 +2304,15 @@ struct mac_iveiv_entry { + #define RFCSR1_TX1_PD FIELD8(0x20) + #define RFCSR1_RX2_PD FIELD8(0x40) + #define RFCSR1_TX2_PD FIELD8(0x80) ++#define RFCSR1_TX2_EN_MT7620 FIELD8(0x02) + + /* + * RFCSR 2: + */ + #define RFCSR2_RESCAL_BP FIELD8(0x40) + #define RFCSR2_RESCAL_EN FIELD8(0x80) ++#define RFCSR2_RX2_EN_MT7620 FIELD8(0x02) ++#define RFCSR2_TX2_EN_MT7620 FIELD8(0x20) + + /* + * RFCSR 3: +@@ -2175,6 +2331,12 @@ struct mac_iveiv_entry { #define RFCSR3_BIT5 FIELD8(0x20) /* @@ -258,7 +298,68 @@ Signed-off-by: Daniel Golle * FRCSR 5: */ #define RFCSR5_R1 FIELD8(0x0c) -@@ -2450,6 +2600,7 @@ enum rt2800_eeprom_word { +@@ -2229,6 +2391,7 @@ struct mac_iveiv_entry { + */ + #define RFCSR13_TX_POWER FIELD8(0x1f) + #define RFCSR13_DR0 FIELD8(0xe0) ++#define RFCSR13_RDIV_MT7620 FIELD8(0x03) + + /* + * RFCSR 15: +@@ -2239,6 +2402,8 @@ struct mac_iveiv_entry { + * RFCSR 16: + */ + #define RFCSR16_TXMIXER_GAIN FIELD8(0x07) ++#define RFCSR16_RF_PLL_FREQ_SEL_MT7620 FIELD8(0x0F) ++#define RFCSR16_SDM_MODE_MT7620 FIELD8(0xE0) + + /* + * RFCSR 17: +@@ -2251,6 +2416,8 @@ struct mac_iveiv_entry { + /* RFCSR 18 */ + #define RFCSR18_XO_TUNE_BYPASS FIELD8(0x40) + ++/* RFCSR 19 */ ++#define RFCSR19_K FIELD8(0x03) + + /* + * RFCSR 20: +@@ -2261,11 +2428,14 @@ struct mac_iveiv_entry { + * RFCSR 21: + */ + #define RFCSR21_RX_LO2_EN FIELD8(0x08) ++#define RFCSR21_BIT1 FIELD8(0x01) ++#define RFCSR21_BIT8 FIELD8(0x80) + + /* + * RFCSR 22: + */ + #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) ++#define RFCSR22_FREQPLAN_D_MT7620 FIELD8(0x07) + + /* + * RFCSR 23: +@@ -2288,6 +2458,11 @@ struct mac_iveiv_entry { + #define RFCSR27_R4 FIELD8(0x40) + + /* ++ * RFCSR 28: ++ */ ++#define RFCSR28_CH11_HT40 FIELD8(0x04) ++ ++/* + * RFCSR 29: + */ + #define RFCSR29_ADC6_TEST FIELD8(0x01) +@@ -2348,6 +2523,7 @@ struct mac_iveiv_entry { + */ + #define RFCSR42_BIT1 FIELD8(0x01) + #define RFCSR42_BIT4 FIELD8(0x08) ++#define RFCSR42_TX2_EN_MT7620 FIELD8(0x40) + + /* + * RFCSR 49: +@@ -2450,6 +2626,7 @@ enum rt2800_eeprom_word { EEPROM_TSSI_BOUND_BG5, EEPROM_TXPOWER_A1, EEPROM_TXPOWER_A2, @@ -266,6 +367,17 @@ Signed-off-by: Daniel Golle EEPROM_TSSI_BOUND_A1, EEPROM_TSSI_BOUND_A2, EEPROM_TSSI_BOUND_A3, +@@ -3019,6 +3196,10 @@ enum rt2800_eeprom_word { + struct rt2800_drv_data { + u8 calibration_bw20; + u8 calibration_bw40; ++ char rx_calibration_bw20; ++ char rx_calibration_bw40; ++ char tx_calibration_bw20; ++ char tx_calibration_bw40; + u8 bbp25; + u8 bbp26; + u8 txmixer_gain_24g; --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c @@ -60,6 +60,9 @@ @@ -288,8 +400,8 @@ Signed-off-by: Daniel Golle - rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); - rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); - rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); -+ switch (rt2x00dev->chip.rf) { -+ case RF7620: ++ switch (rt2x00dev->chip.rt) { ++ case RT6352: + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { + reg = 0; + rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); @@ -351,8 +463,8 @@ Signed-off-by: Daniel Golle - rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); - rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); - rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); -+ switch (rt2x00dev->chip.rf) { -+ case RF7620: ++ switch (rt2x00dev->chip.rt) { ++ case RT6352: + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) { + reg = 0; + rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, @@ -367,11 +479,11 @@ Signed-off-by: Daniel Golle - } + WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®); + } - -- *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); ++ + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620); + break; -+ + +- *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); + default: + if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { + reg = 0; @@ -408,24 +520,25 @@ Signed-off-by: Daniel Golle [EEPROM_TSSI_BOUND_A1] = 0x006a, [EEPROM_TSSI_BOUND_A2] = 0x006b, [EEPROM_TSSI_BOUND_A3] = 0x006c, -@@ -526,6 +593,16 @@ void rt2800_get_txwi_rxwi_size(struct rt - *rxwi_size = RXWI_DESC_SIZE_5WORDS; +@@ -527,6 +594,7 @@ void rt2800_get_txwi_rxwi_size(struct rt break; -+ case RT5390: -+ if (rt2x00dev->chip.rf == RF7620) { -+ *txwi_size = TXWI_DESC_SIZE_5WORDS; -+ *rxwi_size = RXWI_DESC_SIZE_6WORDS; -+ } else { -+ *txwi_size = TXWI_DESC_SIZE_4WORDS; -+ *rxwi_size = RXWI_DESC_SIZE_4WORDS; -+ } -+ break; -+ case RT5592: ++ case RT6352: *txwi_size = TXWI_DESC_SIZE_5WORDS; *rxwi_size = RXWI_DESC_SIZE_6WORDS; -@@ -3258,6 +3335,258 @@ static void rt2800_config_channel_rf55xx + break; +@@ -2964,7 +3032,8 @@ static void rt2800_config_channel_rf53xx + rt2800_rfcsr_write(rt2x00dev, 59, + r59_nonbt_rev[idx]); + } else if (rt2x00_rt(rt2x00dev, RT5390) || +- rt2x00_rt(rt2x00dev, RT5392)) { ++ rt2x00_rt(rt2x00dev, RT5392) || ++ rt2x00_rt(rt2x00dev, RT6352)) { + static const char r59_non_bt[] = {0x8f, 0x8f, + 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, + 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; +@@ -3258,6 +3327,242 @@ static void rt2800_config_channel_rf55xx rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F); } @@ -435,97 +548,85 @@ Signed-off-by: Daniel Golle + struct channel_info *info) +{ + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; -+ u8 txrx_agc_fc; ++ u8 rx_agc_fc, tx_agc_fc; + u8 rfcsr; + + /* Frequeny plan setting */ -+ /* Rdiv setting (stored in rf->rf1) ++ /* Rdiv setting (set 0x03 if Xtal==20) + * R13[1:0] + */ + rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); -+ rfcsr = rfcsr & (~0x03); -+ if (rt2800_clk_is_20mhz(rt2x00dev)) -+ rfcsr |= (rf->rf1 & 0x03); -+ ++ rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620, ++ rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0); + rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); + -+ /* N setting (stored in rf->rf2) -+ * R21[0], R20[7:0] ++ /* N setting ++ * R20[7:0] in rf->rf1 ++ * R21[0] always 0 + */ + rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr); -+ rfcsr = (rf->rf2 & 0x00ff); ++ rfcsr = (rf->rf1 & 0x00ff); + rt2800_rfcsr_write(rt2x00dev, 20, rfcsr); + + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); -+ rfcsr = rfcsr & (~0x01); -+ rfcsr |= ((rf->rf2 & 0x0100) >> 8); ++ rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0); + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); + -+ /* K setting (stored in rf->rf3[0:7]) ++ /* K setting (always 0) + * R16[3:0] (RF PLL freq selection) + */ + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr); -+ rfcsr = rfcsr & (~0x0f); -+ rfcsr |= (rf->rf3 & 0x0f); ++ rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0); + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); + -+ /* D setting (stored in rf->rf3[8:15]) ++ /* D setting (always 0) + * R22[2:0] (D=15, R22[2:0]=<111>) + */ + rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr); -+ rfcsr = rfcsr & (~0x07); -+ rfcsr |= ((rf->rf3 >> 8) & 0x07); ++ rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0); + rt2800_rfcsr_write(rt2x00dev, 22, rfcsr); + -+ /* Ksd setting (stored in rf->rf4) -+ * Ksd: R19<1:0>,R18<7:0>,R17<7:0> ++ /* Ksd setting ++ * Ksd: R17<7:0> in rf->rf2 ++ * R18<7:0> in rf->rf3 ++ * R19<1:0> in rf->rf4 + */ + rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); -+ rfcsr = (rf->rf4 & 0x000000ff); ++ rfcsr = rf->rf2; + rt2800_rfcsr_write(rt2x00dev, 17, rfcsr); + + rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr); -+ rfcsr = ((rf->rf4 & 0x0000ff00) >> 8); ++ rfcsr = rf->rf3; + rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); + + rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr); -+ rfcsr = rfcsr & (~0x03); -+ rfcsr |= ((rf->rf4 & 0x00030000) >> 16); ++ rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4); + rt2800_rfcsr_write(rt2x00dev, 19, rfcsr); + + /* Default: XO=20MHz , SDM mode */ + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr); -+ rfcsr = rfcsr & (~0xE0); -+ rfcsr |= 0x80; ++ rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80); + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr); + + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr); -+ rfcsr |= 0x80; ++ rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1); + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr); + + rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); -+ if (rt2x00dev->default_ant.tx_chain_num == 1) -+ rfcsr &= (~0x2); -+ else -+ rfcsr |= 0x2; ++ rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620, ++ rt2x00dev->default_ant.tx_chain_num != 1); + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); + + rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); -+ if (rt2x00dev->default_ant.tx_chain_num == 1) -+ rfcsr &= (~0x20); -+ else -+ rfcsr |= 0x20; -+ if (rt2x00dev->default_ant.rx_chain_num == 1) -+ rfcsr &= (~0x02); -+ else -+ rfcsr |= 0x02; ++ rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620, ++ rt2x00dev->default_ant.tx_chain_num != 1); ++ rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620, ++ rt2x00dev->default_ant.rx_chain_num != 1); + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); + + rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr); -+ if (rt2x00dev->default_ant.tx_chain_num == 1) -+ rfcsr &= (~0x40); -+ else -+ rfcsr |= 0x40; ++ rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620, ++ rt2x00dev->default_ant.tx_chain_num != 1); + rt2800_rfcsr_write(rt2x00dev, 42, rfcsr); + + /* RF for DC Cal BW */ @@ -552,54 +653,50 @@ Signed-off-by: Daniel Golle + } + + rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr); -+ if (conf_is_ht40(conf) && (rf->channel == 11)) -+ rfcsr |= 0x4; -+ else -+ rfcsr &= (~0x4); ++ rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40, ++ conf_is_ht40(conf) && (rf->channel == 11)); + rt2800_rfcsr_write(rt2x00dev, 28, rfcsr); + + if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) { + if (conf_is_ht40(conf)) { -+ txrx_agc_fc = rt2x00_get_field8( -+ drv_data->calibration_bw40, -+ RFCSR24_TX_AGC_FC); ++ rx_agc_fc = drv_data->rx_calibration_bw40; ++ tx_agc_fc = drv_data->tx_calibration_bw40; + } else { -+ txrx_agc_fc = rt2x00_get_field8( -+ drv_data->calibration_bw20, -+ RFCSR24_TX_AGC_FC); ++ rx_agc_fc = drv_data->rx_calibration_bw20; ++ tx_agc_fc = drv_data->tx_calibration_bw20; + } + rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr); + rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr); + rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr); + rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= rx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr); + + rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr); + rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr); + rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr); + rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr); + rfcsr &= (~0x3F); -+ rfcsr |= txrx_agc_fc; ++ rfcsr |= tx_agc_fc; + rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr); + } +} @@ -684,7 +781,7 @@ Signed-off-by: Daniel Golle static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev, const unsigned int word, const u8 value) -@@ -3414,7 +3743,7 @@ static void rt2800_config_channel(struct +@@ -3414,7 +3719,7 @@ static void rt2800_config_channel(struct struct channel_info *info) { u32 reg; @@ -693,7 +790,7 @@ Signed-off-by: Daniel Golle u8 bbp, rfcsr; info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel, -@@ -3468,6 +3797,9 @@ static void rt2800_config_channel(struct +@@ -3468,6 +3773,9 @@ static void rt2800_config_channel(struct case RF5592: rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info); break; @@ -703,16 +800,26 @@ Signed-off-by: Daniel Golle default: rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info); } -@@ -3574,7 +3906,7 @@ static void rt2800_config_channel(struct +@@ -3551,7 +3859,8 @@ static void rt2800_config_channel(struct + + if (rf->channel <= 14) { + if (!rt2x00_rt(rt2x00dev, RT5390) && +- !rt2x00_rt(rt2x00dev, RT5392)) { ++ !rt2x00_rt(rt2x00dev, RT5392) && ++ !rt2x00_rt(rt2x00dev, RT6352)) { + if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { + rt2800_bbp_write(rt2x00dev, 82, 0x62); + rt2800_bbp_write(rt2x00dev, 82, 0x62); +@@ -3574,7 +3883,7 @@ static void rt2800_config_channel(struct else if (rt2x00_rt(rt2x00dev, RT3593) || rt2x00_rt(rt2x00dev, RT3883)) rt2800_bbp_write(rt2x00dev, 82, 0x82); - else -+ else if (rt2x00dev->chip.rf != RF7620) ++ else if (!rt2x00_rt(rt2x00dev, RT6352)) rt2800_bbp_write(rt2x00dev, 82, 0xf2); if (rt2x00_rt(rt2x00dev, RT3593) || -@@ -3596,7 +3928,7 @@ static void rt2800_config_channel(struct +@@ -3596,7 +3905,7 @@ static void rt2800_config_channel(struct if (rt2x00_rt(rt2x00dev, RT3572)) rt2800_rfcsr_write(rt2x00dev, 8, 0); @@ -721,7 +828,7 @@ Signed-off-by: Daniel Golle switch (rt2x00dev->default_ant.tx_chain_num) { case 3: -@@ -3645,6 +3977,7 @@ static void rt2800_config_channel(struct +@@ -3645,6 +3954,7 @@ static void rt2800_config_channel(struct rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); @@ -729,21 +836,20 @@ Signed-off-by: Daniel Golle rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); -@@ -3720,7 +4053,8 @@ static void rt2800_config_channel(struct +@@ -3720,7 +4030,7 @@ static void rt2800_config_channel(struct usleep_range(1000, 1500); } - if (rt2x00_rt(rt2x00dev, RT5592)) { -+ if (rt2x00_rt(rt2x00dev, RT5592) || -+ (rt2x00_rt(rt2x00dev, RT5390) && rt2x00_rf(rt2x00dev, RF7620))) { ++ if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) { rt2800_bbp_write(rt2x00dev, 195, 141); rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a); -@@ -4410,6 +4744,128 @@ static void rt2800_config_txpower_rt3593 +@@ -4410,6 +4720,128 @@ static void rt2800_config_txpower_rt3593 (unsigned long) regs[i]); } -+static void rt2800_config_txpower_mt7620(struct rt2x00_dev *rt2x00dev, ++static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, + struct ieee80211_channel *chan, + int power_level) +{ @@ -761,7 +867,7 @@ Signed-off-by: Daniel Golle + rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n", + delta); + -+ /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT40, limit ++ /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit + * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor + * driver does as well, though it looks kinda wrong. + * Maybe some misunderstanding of what a signed 8-bit value is? Maybe @@ -827,9 +933,9 @@ Signed-off-by: Daniel Golle + /* Aparently Ralink ran out of space in the BYRATE calibration section + * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x + * registers. As recent 2T chips use 8-bit instead of 4-bit values for -+ * power-offsets more space would be needed. Ralink decided to rather -+ * keep the EEPROM layout untouched and rather have some shared values -+ * covering multiple bitrates. ++ * power-offsets more space would be needed. Ralink decided to keep the ++ * EEPROM layout untouched and rather have some shared values covering ++ * multiple bitrates. + * Populate the registers not covered by the EEPROM in the same way the + * vendor driver does. + */ @@ -868,16 +974,16 @@ Signed-off-by: Daniel Golle /* * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values, -@@ -4607,6 +5063,8 @@ static void rt2800_config_txpower(struct +@@ -4607,6 +5039,8 @@ static void rt2800_config_txpower(struct if (rt2x00_rt(rt2x00dev, RT3593) || rt2x00_rt(rt2x00dev, RT3883)) rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level); -+ else if (rt2x00_rf(rt2x00dev, RF7620)) -+ rt2800_config_txpower_mt7620(rt2x00dev, chan, power_level); ++ else if (rt2x00_rt(rt2x00dev, RT6352)) ++ rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level); else rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level); } -@@ -4622,6 +5080,7 @@ void rt2800_vco_calibration(struct rt2x0 +@@ -4622,6 +5056,7 @@ void rt2800_vco_calibration(struct rt2x0 { u32 tx_pin; u8 rfcsr; @@ -885,7 +991,7 @@ Signed-off-by: Daniel Golle /* * A voltage-controlled oscillator(VCO) is an electronic oscillator -@@ -4661,6 +5120,15 @@ void rt2800_vco_calibration(struct rt2x0 +@@ -4661,6 +5096,15 @@ void rt2800_vco_calibration(struct rt2x0 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1); rt2800_rfcsr_write(rt2x00dev, 3, rfcsr); @@ -901,7 +1007,7 @@ Signed-off-by: Daniel Golle break; default: WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration", -@@ -4668,7 +5136,8 @@ void rt2800_vco_calibration(struct rt2x0 +@@ -4668,7 +5112,8 @@ void rt2800_vco_calibration(struct rt2x0 return; } @@ -911,11 +1017,11 @@ Signed-off-by: Daniel Golle rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); if (rt2x00dev->rf_channel <= 14) { -@@ -4700,6 +5169,42 @@ void rt2800_vco_calibration(struct rt2x0 +@@ -4700,6 +5145,42 @@ void rt2800_vco_calibration(struct rt2x0 } rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); -+ if (rt2x00_rf(rt2x00dev, RF7620)) { ++ if (rt2x00_rt(rt2x00dev, RT6352)) { + if (rt2x00dev->default_ant.tx_chain_num == 1) { + rt2800_bbp_write(rt2x00dev, 91, 0x07); + rt2800_bbp_write(rt2x00dev, 95, 0x1A); @@ -954,11 +1060,31 @@ Signed-off-by: Daniel Golle } EXPORT_SYMBOL_GPL(rt2800_vco_calibration); -@@ -5037,6 +5542,24 @@ static int rt2800_init_registers(struct - rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); +@@ -4798,7 +5279,8 @@ static u8 rt2800_get_default_vgc(struct + rt2x00_rt(rt2x00dev, RT3593) || + rt2x00_rt(rt2x00dev, RT5390) || + rt2x00_rt(rt2x00dev, RT5392) || +- rt2x00_rt(rt2x00dev, RT5592)) ++ rt2x00_rt(rt2x00dev, RT5592) || ++ rt2x00_rt(rt2x00dev, RT6352)) + vgc = 0x1c + (2 * rt2x00dev->lna_gain); + else + vgc = 0x2e + rt2x00dev->lna_gain; +@@ -5038,7 +5520,8 @@ static int rt2800_init_registers(struct rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); -+ } else if (rt2x00_rf(rt2x00dev, RF7620)) { + } else if (rt2x00_rt(rt2x00dev, RT5390) || +- rt2x00_rt(rt2x00dev, RT5392)) { ++ rt2x00_rt(rt2x00dev, RT5392) || ++ rt2x00_rt(rt2x00dev, RT6352)) { + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); +@@ -5048,6 +5531,24 @@ static int rt2800_init_registers(struct + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); + } else if (rt2x00_rt(rt2x00dev, RT5350)) { + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); ++ } else if (rt2x00_rt(rt2x00dev, RT6352)) { + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401); + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000); + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); @@ -976,10 +1102,10 @@ Signed-off-by: Daniel Golle + rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, ®); + rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); + rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); - } else if (rt2x00_rt(rt2x00dev, RT5390) || - rt2x00_rt(rt2x00dev, RT5392)) { - rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); -@@ -6075,6 +6598,224 @@ static void rt2800_init_bbp_5592(struct + } else { + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); +@@ -6075,6 +6576,231 @@ static void rt2800_init_bbp_5592(struct rt2800_bbp_write(rt2x00dev, 103, 0xc0); } @@ -997,7 +1123,14 @@ Signed-off-by: Daniel Golle + rt2800_bbp_write(rt2x00dev, 159, value); +} + -+static void rt2800_init_bbp_7620(struct rt2x00_dev *rt2x00dev) ++static void rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, ++ const u8 reg, u8 *value) ++{ ++ rt2800_bbp_write(rt2x00dev, 158, reg); ++ rt2800_bbp_read(rt2x00dev, 159, value); ++} ++ ++static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev) +{ + u8 bbp; + @@ -1204,23 +1337,364 @@ Signed-off-by: Daniel Golle static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) { unsigned int i; -@@ -6117,7 +6858,10 @@ static void rt2800_init_bbp(struct rt2x0 - return; - case RT5390: - case RT5392: -- rt2800_init_bbp_53xx(rt2x00dev); -+ if (rt2x00dev->chip.rf == RF7620) -+ rt2800_init_bbp_7620(rt2x00dev); -+ else -+ rt2800_init_bbp_53xx(rt2x00dev); - break; +@@ -6122,6 +6848,9 @@ static void rt2800_init_bbp(struct rt2x0 case RT5592: rt2800_init_bbp_5592(rt2x00dev); -@@ -7331,6 +8075,269 @@ static void rt2800_init_rfcsr_5592(struc + return; ++ case RT6352: ++ rt2800_init_bbp_6352(rt2x00dev); ++ break; + } + + for (i = 0; i < EEPROM_BBP_SIZE; i++) { +@@ -7331,6 +8060,615 @@ static void rt2800_init_rfcsr_5592(struc rt2800_led_open_drain_enable(rt2x00dev); } -+static void rt2800_init_rfcsr_7620(struct rt2x00_dev *rt2x00dev) ++static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev, ++ bool set_bw, bool is_ht40) ++{ ++ u8 bbp_val; ++ ++ rt2800_bbp_read(rt2x00dev, 21, &bbp_val); ++ bbp_val |= 0x1; ++ rt2800_bbp_write(rt2x00dev, 21, bbp_val); ++ usleep_range(100, 200); ++ ++ if (set_bw) { ++ rt2800_bbp_read(rt2x00dev, 4, &bbp_val); ++ rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40); ++ rt2800_bbp_write(rt2x00dev, 4, bbp_val); ++ usleep_range(100, 200); ++ } ++ ++ rt2800_bbp_read(rt2x00dev, 21, &bbp_val); ++ bbp_val &= (~0x1); ++ rt2800_bbp_write(rt2x00dev, 21, bbp_val); ++ usleep_range(100, 200); ++} ++ ++static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal) ++{ ++ u8 rf_val; ++ ++ if (btxcal) ++ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04); ++ else ++ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02); ++ ++ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06); ++ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &rf_val); ++ rf_val |= 0x80; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val); ++ ++ if (btxcal) { ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val); ++ rf_val &= (~0x3F); ++ rf_val |= 0x3F; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val); ++ rf_val &= (~0x3F); ++ rf_val |= 0x3F; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31); ++ } else { ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &rf_val); ++ rf_val &= (~0x3F); ++ rf_val |= 0x34; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &rf_val); ++ rf_val &= (~0x3F); ++ rf_val |= 0x34; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val); ++ } ++ ++ return 0; ++} ++ ++static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev) ++{ ++ unsigned int cnt; ++ u8 bbp_val; ++ char cal_val; ++ ++ rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82); ++ ++ cnt = 0; ++ do { ++ usleep_range(500, 2000); ++ rt2800_bbp_read(rt2x00dev, 159, &bbp_val); ++ if (bbp_val == 0x02 || cnt == 20) ++ break; ++ ++ cnt++; ++ } while (cnt < 20); ++ ++ rt2800_bbp_dcoc_read(rt2x00dev, 0x39, &bbp_val); ++ cal_val = bbp_val & 0x7F; ++ if (cal_val >= 0x40) ++ cal_val -= 128; ++ ++ return cal_val; ++} ++ ++static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, ++ bool btxcal) ++{ ++ struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; ++ u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc; ++ u8 filter_target; ++ u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02; ++ u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31; ++ int loop = 0, is_ht40, cnt; ++ u8 bbp_val, rf_val; ++ char cal_r32_init, cal_r32_val, cal_diff; ++ u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05; ++ u8 saverfb5r06, saverfb5r07; ++ u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20; ++ u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41; ++ u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46; ++ u8 saverfb5r58, saverfb5r59; ++ u8 savebbp159r0, savebbp159r2, savebbpr23; ++ u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; ++ ++ /* Save MAC registers */ ++ rt2800_register_read(rt2x00dev, RF_CONTROL0, &MAC_RF_CONTROL0); ++ rt2800_register_read(rt2x00dev, RF_BYPASS0, &MAC_RF_BYPASS0); ++ ++ /* save BBP registers */ ++ rt2800_bbp_read(rt2x00dev, 23, &savebbpr23); ++ ++ rt2800_bbp_dcoc_read(rt2x00dev, 0, &savebbp159r0); ++ rt2800_bbp_dcoc_read(rt2x00dev, 2, &savebbp159r2); ++ ++ /* Save RF registers */ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &saverfb5r00); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &saverfb5r01); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 3, &saverfb5r03); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 4, &saverfb5r04); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 5, &saverfb5r05); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &saverfb5r06); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &saverfb5r07); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &saverfb5r08); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 17, &saverfb5r17); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 18, &saverfb5r18); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 19, &saverfb5r19); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 20, &saverfb5r20); ++ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 37, &saverfb5r37); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 38, &saverfb5r38); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 39, &saverfb5r39); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 40, &saverfb5r40); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 41, &saverfb5r41); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 42, &saverfb5r42); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 43, &saverfb5r43); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 44, &saverfb5r44); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 45, &saverfb5r45); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 46, &saverfb5r46); ++ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &saverfb5r58); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &saverfb5r59); ++ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val); ++ rf_val |= 0x3; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); ++ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val); ++ rf_val |= 0x1; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val); ++ ++ cnt = 0; ++ do { ++ usleep_range(500, 2000); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 1, &rf_val); ++ if (((rf_val & 0x1) == 0x00) || (cnt == 40)) ++ break; ++ cnt++; ++ } while (cnt < 40); ++ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 0, &rf_val); ++ rf_val &= (~0x3); ++ rf_val |= 0x1; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val); ++ ++ /* I-3 */ ++ rt2800_bbp_read(rt2x00dev, 23, &bbp_val); ++ bbp_val &= (~0x1F); ++ bbp_val |= 0x10; ++ rt2800_bbp_write(rt2x00dev, 23, bbp_val); ++ ++ do { ++ /* I-4,5,6,7,8,9 */ ++ if (loop == 0) { ++ is_ht40 = false; ++ ++ if (btxcal) ++ filter_target = tx_filter_target_20m; ++ else ++ filter_target = rx_filter_target_20m; ++ } else { ++ is_ht40 = true; ++ ++ if (btxcal) ++ filter_target = tx_filter_target_40m; ++ else ++ filter_target = rx_filter_target_40m; ++ } ++ ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 8, &rf_val); ++ rf_val &= (~0x04); ++ if (loop == 1) ++ rf_val |= 0x4; ++ ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val); ++ ++ rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40); ++ ++ rt2800_rf_lp_config(rt2x00dev, btxcal); ++ if (btxcal) { ++ tx_agc_fc = 0; ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val); ++ rf_val &= (~0x7F); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val); ++ rf_val &= (~0x7F); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); ++ } else { ++ rx_agc_fc = 0; ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val); ++ rf_val &= (~0x7F); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val); ++ rf_val &= (~0x7F); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); ++ } ++ ++ usleep_range(1000, 2000); ++ ++ rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val); ++ bbp_val &= (~0x6); ++ rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); ++ ++ rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); ++ ++ cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev); ++ ++ rt2800_bbp_dcoc_read(rt2x00dev, 2, &bbp_val); ++ bbp_val |= 0x6; ++ rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val); ++do_cal: ++ if (btxcal) { ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rf_val); ++ rf_val &= (~0x7F); ++ rf_val |= tx_agc_fc; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rf_val); ++ rf_val &= (~0x7F); ++ rf_val |= tx_agc_fc; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val); ++ } else { ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rf_val); ++ rf_val &= (~0x7F); ++ rf_val |= rx_agc_fc; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val); ++ rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rf_val); ++ rf_val &= (~0x7F); ++ rf_val |= rx_agc_fc; ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val); ++ } ++ ++ usleep_range(500, 1000); ++ ++ rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40); ++ ++ cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev); ++ ++ cal_diff = cal_r32_init - cal_r32_val; ++ ++ if (btxcal) ++ cmm_agc_fc = tx_agc_fc; ++ else ++ cmm_agc_fc = rx_agc_fc; ++ ++ if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) || ++ ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) { ++ if (btxcal) ++ tx_agc_fc = 0; ++ else ++ rx_agc_fc = 0; ++ } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) { ++ if (btxcal) ++ tx_agc_fc++; ++ else ++ rx_agc_fc++; ++ goto do_cal; ++ } ++ ++ if (btxcal) { ++ if (loop == 0) ++ drv_data->tx_calibration_bw20 = tx_agc_fc; ++ else ++ drv_data->tx_calibration_bw40 = tx_agc_fc; ++ } else { ++ if (loop == 0) ++ drv_data->rx_calibration_bw20 = rx_agc_fc; ++ else ++ drv_data->rx_calibration_bw40 = rx_agc_fc; ++ } ++ ++ loop++; ++ } while (loop <= 1); ++ ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20); ++ ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46); ++ ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58); ++ rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59); ++ ++ rt2800_bbp_write(rt2x00dev, 23, savebbpr23); ++ ++ rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0); ++ rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2); ++ ++ rt2800_bbp_read(rt2x00dev, 4, &bbp_val); ++ rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, ++ 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)); ++ rt2800_bbp_write(rt2x00dev, 4, bbp_val); ++ ++ rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0); ++ rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0); ++} ++ ++static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev) +{ + /* Initialize RF central register to default value */ + rt2800_rfcsr_write(rt2x00dev, 0, 0x02); @@ -1481,24 +1955,35 @@ Signed-off-by: Daniel Golle + + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00); + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C); ++ ++ rt2800_bw_filter_calibration(rt2x00dev, true); ++ rt2800_bw_filter_calibration(rt2x00dev, false); +} + static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) { if (rt2800_is_305x_soc(rt2x00dev)) { -@@ -7366,7 +8373,10 @@ static void rt2800_init_rfcsr(struct rt2 - rt2800_init_rfcsr_5350(rt2x00dev); +@@ -7374,6 +8712,9 @@ static void rt2800_init_rfcsr(struct rt2 + case RT5592: + rt2800_init_rfcsr_5592(rt2x00dev); break; - case RT5390: -- rt2800_init_rfcsr_5390(rt2x00dev); -+ if (rt2x00dev->chip.rf == RF7620) -+ rt2800_init_rfcsr_7620(rt2x00dev); -+ else -+ rt2800_init_rfcsr_5390(rt2x00dev); - break; - case RT5392: - rt2800_init_rfcsr_5392(rt2x00dev); -@@ -7780,6 +8790,7 @@ static int rt2800_init_eeprom(struct rt2 ++ case RT6352: ++ rt2800_init_rfcsr_6352(rt2x00dev); ++ break; + } + } + +@@ -7745,7 +9086,8 @@ static int rt2800_init_eeprom(struct rt2 + */ + if (rt2x00_rt(rt2x00dev, RT3290) || + rt2x00_rt(rt2x00dev, RT5390) || +- rt2x00_rt(rt2x00dev, RT5392)) ++ rt2x00_rt(rt2x00dev, RT5392) || ++ rt2x00_rt(rt2x00dev, RT6352)) + rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf); + else if (rt2x00_rt(rt2x00dev, RT3352)) + rf = RF3322; +@@ -7780,6 +9122,7 @@ static int rt2800_init_eeprom(struct rt2 case RF5390: case RF5392: case RF5592: @@ -1506,32 +1991,31 @@ Signed-off-by: Daniel Golle break; default: rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n", -@@ -8258,6 +9269,24 @@ static const struct rf_channel rf_vals_5 +@@ -8258,6 +9601,23 @@ static const struct rf_channel rf_vals_5 {196, 83, 0, 12, 1}, }; +static const struct rf_channel rf_vals_7620[] = { -+ /* Channel, Rdiv, N, K | (D >> 8), Ksd */ -+ {1, 3, 0x50, 0 | (0 >> 8), 0x19999}, -+ {2, 3, 0x50, 0 | (0 >> 8), 0x24444}, -+ {3, 3, 0x50, 0 | (0 >> 8), 0x2EEEE}, -+ {4, 3, 0x50, 0 | (0 >> 8), 0x39999}, -+ {5, 3, 0x51, 0 | (0 >> 8), 0x04444}, -+ {6, 3, 0x51, 0 | (0 >> 8), 0x0EEEE}, -+ {7, 3, 0x51, 0 | (0 >> 8), 0x19999}, -+ {8, 3, 0x51, 0 | (0 >> 8), 0x24444}, -+ {9, 3, 0x51, 0 | (0 >> 8), 0x2EEEE}, -+ {10, 3, 0x51, 0 | (0 >> 8), 0x39999}, -+ {11, 3, 0x52, 0 | (0 >> 8), 0x04444}, -+ {12, 3, 0x52, 0 | (0 >> 8), 0x0EEEE}, -+ {13, 3, 0x52, 0 | (0 >> 8), 0x19999}, -+ {14, 3, 0x52, 0 | (0 >> 8), 0x33333}, ++ {1, 0x50, 0x99, 0x99, 1}, ++ {2, 0x50, 0x44, 0x44, 2}, ++ {3, 0x50, 0xEE, 0xEE, 2}, ++ {4, 0x50, 0x99, 0x99, 3}, ++ {5, 0x51, 0x44, 0x44, 0}, ++ {6, 0x51, 0xEE, 0xEE, 0}, ++ {7, 0x51, 0x99, 0x99, 1}, ++ {8, 0x51, 0x44, 0x44, 2}, ++ {9, 0x51, 0xEE, 0xEE, 2}, ++ {10, 0x51, 0x99, 0x99, 3}, ++ {11, 0x52, 0x44, 0x44, 0}, ++ {12, 0x52, 0xEE, 0xEE, 0}, ++ {13, 0x52, 0x99, 0x99, 1}, ++ {14, 0x52, 0x33, 0x33, 3}, +}; + static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) { struct hw_mode_spec *spec = &rt2x00dev->spec; -@@ -8361,6 +9390,11 @@ static int rt2800_probe_hw_mode(struct r +@@ -8361,6 +9721,11 @@ static int rt2800_probe_hw_mode(struct r spec->channels = rf_vals_3x; break; @@ -1543,7 +2027,7 @@ Signed-off-by: Daniel Golle case RF3052: case RF3053: spec->num_channels = ARRAY_SIZE(rf_vals_3x); -@@ -8498,6 +9532,7 @@ static int rt2800_probe_hw_mode(struct r +@@ -8498,6 +9863,7 @@ static int rt2800_probe_hw_mode(struct r case RF5390: case RF5392: case RF5592: @@ -1551,3 +2035,23 @@ Signed-off-by: Daniel Golle __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags); break; } +@@ -8543,6 +9909,9 @@ static int rt2800_probe_rt(struct rt2x00 + return -ENODEV; + } + ++ if (rt == RT5390 && rt2x00_is_soc(rt2x00dev)) ++ rt = RT6352; ++ + rt2x00_set_rt(rt2x00dev, rt, rev); + + return 0; +--- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h ++++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h +@@ -175,6 +175,7 @@ struct rt2x00_chip { + #define RT5390 0x5390 /* 2.4GHz */ + #define RT5392 0x5392 /* 2.4GHz */ + #define RT5592 0x5592 ++#define RT6352 0x6352 /* WSOC 2.4GHz */ + + u16 rf; + u16 rev;