Fix endianness issues with adm5120eb, thanks to Gabor !
SVN-Revision: 7479
This commit is contained in:
Florian Fainelli
parent
7b071f1bfc
commit
c2990fa19e
112
package/acx/patches/003-endianness-fixes.patch
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112
package/acx/patches/003-endianness-fixes.patch
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@ -0,0 +1,112 @@
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diff -Nur -x '*.o' -x '*.ko' acx-20070101/pci.c acx-20070101.big/pci.c
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--- acx-20070101/pci.c 2007-06-02 17:29:53.000000000 +0200
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+++ acx-20070101.big/pci.c 2007-06-02 17:23:37.000000000 +0200
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@@ -123,6 +123,11 @@
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** Register access
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*/
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+#define acx_readl(v) le32_to_cpu(readl((v)))
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+#define acx_readw(v) le16_to_cpu(readw((v)))
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+#define acx_writew(v,r) writew(le16_to_cpu((v)), r)
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+#define acx_writel(v,r) writel(le32_to_cpu((v)), r)
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+
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/* Pick one */
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/* #define INLINE_IO static */
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#define INLINE_IO static inline
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@@ -131,17 +136,17 @@
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read_reg32(acx_device_t *adev, unsigned int offset)
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{
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#if ACX_IO_WIDTH == 32
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- return readl((u8 *)adev->iobase + adev->io[offset]);
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+ return acx_readl((u8 *)adev->iobase + adev->io[offset]);
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#else
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- return readw((u8 *)adev->iobase + adev->io[offset])
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- + (readw((u8 *)adev->iobase + adev->io[offset] + 2) << 16);
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+ return acx_readw((u8 *)adev->iobase + adev->io[offset])
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+ + (acx_readw((u8 *)adev->iobase + adev->io[offset] + 2) << 16);
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#endif
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}
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INLINE_IO u16
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read_reg16(acx_device_t *adev, unsigned int offset)
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{
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- return readw((u8 *)adev->iobase + adev->io[offset]);
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+ return acx_readw((u8 *)adev->iobase + adev->io[offset]);
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}
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INLINE_IO u8
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@@ -154,17 +159,17 @@
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write_reg32(acx_device_t *adev, unsigned int offset, u32 val)
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{
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#if ACX_IO_WIDTH == 32
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- writel(val, (u8 *)adev->iobase + adev->io[offset]);
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+ acx_writel(val, (u8 *)adev->iobase + adev->io[offset]);
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#else
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- writew(val & 0xffff, (u8 *)adev->iobase + adev->io[offset]);
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- writew(val >> 16, (u8 *)adev->iobase + adev->io[offset] + 2);
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+ acx_writew(val & 0xffff, (u8 *)adev->iobase + adev->io[offset]);
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+ acx_writew(val >> 16, (u8 *)adev->iobase + adev->io[offset] + 2);
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#endif
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}
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INLINE_IO void
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write_reg16(acx_device_t *adev, unsigned int offset, u16 val)
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{
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- writew(val, (u8 *)adev->iobase + adev->io[offset]);
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+ acx_writew(val, (u8 *)adev->iobase + adev->io[offset]);
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}
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INLINE_IO void
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@@ -192,7 +197,7 @@
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{
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/* fast version (accesses the first register, IO_ACX_SOFT_RESET,
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* which should be safe): */
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- return readl(adev->iobase) != 0xffffffff;
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+ return acx_readl(adev->iobase) != 0xffffffff;
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}
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@@ -835,7 +840,7 @@
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static inline void
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acxpci_write_cmd_type_status(acx_device_t *adev, u16 type, u16 status)
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{
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- writel(type | (status << 16), adev->cmd_area);
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+ acx_writel(type | (status << 16), adev->cmd_area);
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write_flush(adev);
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}
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@@ -848,7 +853,7 @@
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{
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u32 cmd_type, cmd_status;
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- cmd_type = readl(adev->cmd_area);
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+ cmd_type = acx_readl(adev->cmd_area);
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cmd_status = (cmd_type >> 16);
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cmd_type = (u16)cmd_type;
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@@ -2415,12 +2420,12 @@
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#endif
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u32 info_type, info_status;
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- info_type = readl(adev->info_area);
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+ info_type = acx_readl(adev->info_area);
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info_status = (info_type >> 16);
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info_type = (u16)info_type;
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/* inform fw that we have read this info message */
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- writel(info_type | 0x00010000, adev->info_area);
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+ acx_writel(info_type | 0x00010000, adev->info_area);
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write_reg16(adev, IO_ACX_INT_TRIG, INT_TRIG_INFOACK);
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write_flush(adev);
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@@ -4209,8 +4214,8 @@
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#define ENDIANNESS_STRING "running on a BIG-ENDIAN CPU\n"
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#endif
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log(L_INIT,
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- ENDIANNESS_STRING
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- "PCI module " ACX_RELEASE " initialized, "
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+ "acx: " ENDIANNESS_STRING
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+ "acx: PCI module " ACX_RELEASE " initialized, "
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"waiting for cards to probe...\n"
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);
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@ -26,54 +26,105 @@
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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volatile u32* pci_config_address_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR);
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volatile u32* pci_config_data_reg = (volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA);
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#define DEBUG 0
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#if DEBUG
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#define DBG(f, ...) printk(f, ## __VA_ARGS__ )
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#else
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#define DBG(f, ...)
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#endif
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#define PCI_ENABLE 0x80000000
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *val)
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static inline void write_cfgaddr(u32 addr)
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{
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*pci_config_address_reg = ((bus->number & 0xff) << 0x10) |
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((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE;
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*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_ADDR) = (addr | PCI_ENABLE);
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}
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static inline void write_cfgdata(u32 data)
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{
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*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA) = data;
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}
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static inline u32 read_cfgdata(void)
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{
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return (*(volatile u32*)KSEG1ADDR(ADM5120_PCICFG_DATA));
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}
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static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
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{
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return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
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(where & 0xFC));
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}
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static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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u32 data;
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_read %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
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switch (size) {
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case 1:
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*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xff;
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if (where & 1)
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data >>= 8;
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if (where & 2)
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data >>= 16;
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data &= 0xFF;
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break;
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case 2:
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*val = ((*pci_config_data_reg)>>((where&3)<<3))&0xffff;
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break;
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default:
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*val = (*pci_config_data_reg);
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if (where & 2)
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data >>= 16;
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data &= 0xFFFF;
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break;
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}
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*val = data;
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DBG(", 0x%08X returned\n", data);
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return PCIBIOS_SUCCESSFUL;
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}
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static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t val)
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int size, u32 val)
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{
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*pci_config_address_reg = ((bus->number & 0xff) << 0x10) |
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((devfn & 0xff) << 0x08) | (where & 0xfc) | PCI_ENABLE;
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u32 data;
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int s;
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write_cfgaddr(mkaddr(bus,devfn,where));
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data = read_cfgdata();
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DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
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bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, data);
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switch (size) {
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case 1:
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*(volatile u8 *)(((int)pci_config_data_reg) +
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(where & 3)) = val;
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s = ((where & 3) << 3);
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data &= ~(0xFF << s);
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data |= ((val & 0xFF) << s);
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break;
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case 2:
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*(volatile u16 *)(((int)pci_config_data_reg) +
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(where & 2)) = (val);
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s = ((where & 2) << 4);
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data &= ~(0xFFFF << s);
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data |= ((val & 0xFFFF) << s);
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break;
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case 4:
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data = val;
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break;
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default:
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*pci_config_data_reg = (val);
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}
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write_cfgdata(data);
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DBG(", 0x%08X written\n", data);
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return PCIBIOS_SUCCESSFUL;
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}
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