atheros: indent fixes
Various indent fixes suggested by checkpatch: use tabs, use same level of indentation for switch and case, correct indentation levels. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> SVN-Revision: 41090
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@ -197,15 +197,15 @@
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+
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+ /* AR2316 relocates radio config to new location */
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+ if (!found) {
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+ for (radio_config = board_config + 0xf8;
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+ (radio_config < flash_limit - 0x1000 + 0xf8);
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+ radio_config += 0x1000) {
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+ for (radio_config = board_config + 0xf8;
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+ (radio_config < flash_limit - 0x1000 + 0xf8);
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+ radio_config += 0x1000) {
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+ if ((*(u32 *)radio_config != 0xffffffff) &&
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+ check_radio_magic(radio_config)) {
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+ check_radio_magic(radio_config)) {
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+ found = 1;
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+ break;
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+ }
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+ }
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+ }
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+ }
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+
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+ if (!found) {
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@ -398,15 +398,15 @@
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+ * address(es).
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+ */
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+struct ar231x_boarddata {
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+ u32 magic; /* board data is valid */
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+ u32 magic; /* board data is valid */
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+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
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+ u16 cksum; /* checksum (starting with BD_REV 2) */
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+ u16 rev; /* revision of this struct */
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+#define BD_REV 4
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+ char board_name[64]; /* Name of board */
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+ u16 major; /* Board major number */
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+ u16 minor; /* Board minor number */
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+ u32 flags; /* Board configuration */
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+ u16 cksum; /* checksum (starting with BD_REV 2) */
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+ u16 rev; /* revision of this struct */
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+#define BD_REV 4
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+ char board_name[64]; /* Name of board */
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+ u16 major; /* Board major number */
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+ u16 minor; /* Board minor number */
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+ u32 flags; /* Board configuration */
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+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
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+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
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+#define BD_UART1 0x00000004 /* UART1 is stuffed */
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@ -425,22 +425,22 @@
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+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
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+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
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+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
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+ u16 reset_config_gpio; /* Reset factory GPIO pin */
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+ u16 sys_led_gpio; /* System LED GPIO pin */
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+ u16 reset_config_gpio; /* Reset factory GPIO pin */
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+ u16 sys_led_gpio; /* System LED GPIO pin */
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+
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+ u32 cpu_freq; /* CPU core frequency in Hz */
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+ u32 sys_freq; /* System frequency in Hz */
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+ u32 cnt_freq; /* Calculated C0_COUNT frequency */
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+ u32 cpu_freq; /* CPU core frequency in Hz */
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+ u32 sys_freq; /* System frequency in Hz */
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+ u32 cnt_freq; /* Calculated C0_COUNT frequency */
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+
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+ u8 wlan0_mac[6];
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+ u8 enet0_mac[6];
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+ u8 enet1_mac[6];
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+ u8 wlan0_mac[6];
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+ u8 enet0_mac[6];
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+ u8 enet1_mac[6];
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+
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+ u16 pci_id; /* Pseudo PCIID for common code */
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+ u16 mem_cap; /* cap bank1 in MB */
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+ u16 pci_id; /* Pseudo PCIID for common code */
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+ u16 mem_cap; /* cap bank1 in MB */
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+
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+ /* version 3 */
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+ u8 wlan1_mac[6]; /* (ar5212) */
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+ /* version 3 */
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+ u8 wlan1_mac[6]; /* (ar5212) */
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+};
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+
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+#define BOARD_CONFIG_BUFSZ 0x1000
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@ -932,10 +932,10 @@
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+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
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+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
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+
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+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
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+ /* write 1 to clear all bits in ERR0 */
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+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
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+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
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+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
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+ /* write 1 to clear all bits in ERR0 */
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+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
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+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
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+
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+#define AR2315_PROCERR_HMAST 0x0000000f
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+#define AR2315_PROCERR_HMAST_DFLT 0
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@ -1292,7 +1292,7 @@
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+#endif /* __AR2315_REG_H */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
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@@ -0,0 +1,232 @@
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@@ -0,0 +1,233 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -1355,18 +1355,18 @@
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+/* Reset/Timer Block Address Map */
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+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
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+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
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+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
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+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
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+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
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+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
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+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
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+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
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+#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
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+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
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+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
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+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
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+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
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+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
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+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
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+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
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+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
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+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
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+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
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+
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+/* AR531X_WD_CTRL register bit field definitions */
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@ -1444,7 +1444,8 @@
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+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
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+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
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+#define AR531X_ENABLE_WLAN1 \
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+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
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+ (AR531X_ENABLE_UART_AND_WLAN1_PIO |\
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+ AR531X_ENABLE_WLAN1_DMA)
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+
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+/* AR531X_REV register bit field definitions */
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+#define AR531X_REV_WMAC_MAJ 0xf000
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@ -2080,8 +2081,8 @@
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+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
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+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
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+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
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+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
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+ + (bank1AC ? (1 << (bank1AC+1)) : 0);
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+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
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+ (bank1AC ? (1 << (bank1AC+1)) : 0);
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+ memsize <<= 20;
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+ add_memory_region(0, memsize, BOOT_MEM_RAM);
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+
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@ -2109,7 +2110,7 @@
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+
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--- /dev/null
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+++ b/arch/mips/ar231x/ar2315.c
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@@ -0,0 +1,691 @@
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@@ -0,0 +1,693 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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@ -2259,23 +2260,23 @@
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+ imr = ar231x_read_reg(AR2315_IMR);
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+ switch(d->irq) {
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+ case AR531X_MISC_IRQ_SPI:
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+ imr |= AR2315_ISR_SPI;
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+ break;
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+ imr |= AR2315_ISR_SPI;
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+ break;
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+ case AR531X_MISC_IRQ_TIMER:
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+ imr |= AR2315_ISR_TIMER;
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+ break;
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+ imr |= AR2315_ISR_TIMER;
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+ break;
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+ case AR531X_MISC_IRQ_AHB_PROC:
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+ imr |= AR2315_ISR_AHB;
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+ break;
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+ imr |= AR2315_ISR_AHB;
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+ break;
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+ case AR531X_MISC_IRQ_GPIO:
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+ imr |= AR2315_ISR_GPIO;
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+ break;
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+ imr |= AR2315_ISR_GPIO;
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+ break;
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+ case AR531X_MISC_IRQ_UART0:
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+ imr |= AR2315_ISR_UART0;
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+ break;
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+ imr |= AR2315_ISR_UART0;
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+ break;
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+ case AR531X_MISC_IRQ_WATCHDOG:
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+ imr |= AR2315_ISR_WD;
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+ break;
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+ imr |= AR2315_ISR_WD;
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+ break;
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+ default:
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+ break;
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+ }
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@ -2290,23 +2291,23 @@
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+ imr = ar231x_read_reg(AR2315_IMR);
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+ switch(d->irq) {
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+ case AR531X_MISC_IRQ_SPI:
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+ imr &= ~AR2315_ISR_SPI;
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+ break;
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+ imr &= ~AR2315_ISR_SPI;
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+ break;
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+ case AR531X_MISC_IRQ_TIMER:
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+ imr &= ~AR2315_ISR_TIMER;
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+ break;
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+ imr &= ~AR2315_ISR_TIMER;
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+ break;
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+ case AR531X_MISC_IRQ_AHB_PROC:
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+ imr &= ~AR2315_ISR_AHB;
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+ break;
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+ imr &= ~AR2315_ISR_AHB;
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+ break;
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+ case AR531X_MISC_IRQ_GPIO:
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+ imr &= ~AR2315_ISR_GPIO;
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+ break;
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+ imr &= ~AR2315_ISR_GPIO;
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+ break;
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+ case AR531X_MISC_IRQ_UART0:
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+ imr &= ~AR2315_ISR_UART0;
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+ break;
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+ imr &= ~AR2315_ISR_UART0;
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+ break;
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+ case AR531X_MISC_IRQ_WATCHDOG:
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+ imr &= ~AR2315_ISR_WD;
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+ break;
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+ imr &= ~AR2315_ISR_WD;
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+ break;
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+ default:
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+ break;
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+ }
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@ -2320,13 +2321,13 @@
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+
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+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
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+{
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+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
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+ ar231x_read_reg(AR2315_AHB_ERR1);
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+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
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+ ar231x_read_reg(AR2315_AHB_ERR1);
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+
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+ pr_emerg("AHB fatal error\n");
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+ machine_restart("AHB error"); /* Catastrophic failure */
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+ pr_emerg("AHB fatal error\n");
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+ machine_restart("AHB error"); /* Catastrophic failure */
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+
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+ return IRQ_HANDLED;
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+ return IRQ_HANDLED;
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+}
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+
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+static struct irqaction ar2315_ahb_proc_interrupt = {
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@ -2560,22 +2561,22 @@
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+ u32 flash_size = 0;
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+
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+ /* probe the flash chip size */
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+ switch(spiflash_probe()) {
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+ case STM_8MBIT_SIGNATURE:
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+ flash_size = 0x00100000;
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+ break;
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+ case STM_16MBIT_SIGNATURE:
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+ flash_size = 0x00200000;
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+ break;
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+ case STM_32MBIT_SIGNATURE:
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+ flash_size = 0x00400000;
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+ break;
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+ case STM_64MBIT_SIGNATURE:
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+ flash_size = 0x00800000;
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+ break;
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+ case STM_128MBIT_SIGNATURE:
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+ flash_size = 0x01000000;
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+ break;
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+ switch (spiflash_probe()) {
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+ case STM_8MBIT_SIGNATURE:
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+ flash_size = 0x00100000;
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+ break;
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+ case STM_16MBIT_SIGNATURE:
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+ flash_size = 0x00200000;
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+ break;
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+ case STM_32MBIT_SIGNATURE:
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+ flash_size = 0x00400000;
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+ break;
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+ case STM_64MBIT_SIGNATURE:
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+ flash_size = 0x00800000;
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+ break;
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+ case STM_128MBIT_SIGNATURE:
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+ flash_size = 0x01000000;
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+ break;
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+ }
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+
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+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
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@ -2693,19 +2694,21 @@
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+ divby2 += 1;
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+ pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
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+
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+ /* clkm input selected */
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+ /* clkm input selected */
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+ switch (clock_ctl & CPUCLK_CLK_SEL_M) {
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+ case 0:
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+ case 1:
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+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
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+ break;
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+ case 2:
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+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
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+ break;
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+ default:
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+ pllc_out = 40000000;
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+ clk_div = 1;
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+ break;
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+ case 0:
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+ case 1:
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+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
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+ PLLC_CLKM_DIV_S];
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+ break;
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+ case 2:
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+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
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+ PLLC_CLKC_DIV_S];
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+ break;
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+ default:
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+ pllc_out = 40000000;
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+ clk_div = 1;
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+ break;
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+ }
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+
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+ cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
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@ -2717,13 +2720,13 @@
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+static inline unsigned int
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+ar2315_cpu_frequency(void)
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+{
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+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
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+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
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+}
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+
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+static inline unsigned int
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+ar2315_apb_frequency(void)
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+{
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+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
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+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
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+}
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+
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+void __init
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@ -2770,14 +2773,14 @@
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+
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+ /* Detect the hardware based on the device ID */
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+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
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+ switch(devid) {
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+ case 0x90:
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+ case 0x91:
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+ ar231x_devtype = DEV_TYPE_AR2317;
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+ break;
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+ default:
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+ ar231x_devtype = DEV_TYPE_AR2315;
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+ break;
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+ switch (devid) {
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+ case 0x90:
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+ case 0x91:
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+ ar231x_devtype = DEV_TYPE_AR2317;
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+ break;
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+ default:
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+ ar231x_devtype = DEV_TYPE_AR2315;
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+ break;
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+ }
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+ ar2315_gpio_init();
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+ ar231x_board.devid = devid;
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@ -32,7 +32,7 @@
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+obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o
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--- /dev/null
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+++ b/drivers/net/ethernet/ar231x/ar231x.c
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@@ -0,0 +1,1256 @@
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@@ -0,0 +1,1255 @@
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+/*
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+ * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
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+ *
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@ -190,23 +190,23 @@
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+static void
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+ar231x_netpoll(struct net_device *dev)
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+{
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+ unsigned long flags;
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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+ ar231x_interrupt(dev->irq, dev);
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+ local_irq_restore(flags);
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+ local_irq_save(flags);
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+ ar231x_interrupt(dev->irq, dev);
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+ local_irq_restore(flags);
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+}
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+#endif
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+
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+static const struct net_device_ops ar231x_ops = {
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+ .ndo_open = ar231x_open,
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+ .ndo_stop = ar231x_close,
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+ .ndo_start_xmit = ar231x_start_xmit,
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+ .ndo_set_rx_mode = ar231x_multicast_list,
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+ .ndo_do_ioctl = ar231x_ioctl,
|
||||
+ .ndo_change_mtu = eth_change_mtu,
|
||||
+ .ndo_open = ar231x_open,
|
||||
+ .ndo_stop = ar231x_close,
|
||||
+ .ndo_start_xmit = ar231x_start_xmit,
|
||||
+ .ndo_set_rx_mode = ar231x_multicast_list,
|
||||
+ .ndo_do_ioctl = ar231x_ioctl,
|
||||
+ .ndo_change_mtu = eth_change_mtu,
|
||||
+ .ndo_validate_addr = eth_validate_addr,
|
||||
+ .ndo_set_mac_address = eth_mac_addr,
|
||||
+ .ndo_set_mac_address = eth_mac_addr,
|
||||
+ .ndo_tx_timeout = ar231x_tx_timeout,
|
||||
+#ifdef CONFIG_NET_POLL_CONTROLLER
|
||||
+ .ndo_poll_controller = ar231x_netpoll,
|
||||
@ -744,7 +744,7 @@
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+ init_error:
|
||||
+init_error:
|
||||
+ ar231x_init_cleanup(dev);
|
||||
+ return ecode;
|
||||
+}
|
||||
@ -1213,8 +1213,7 @@
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
|
||||
+ u16 value)
|
||||
+ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
|
||||
+{
|
||||
+ struct net_device *const dev = bus->priv;
|
||||
+ struct ar231x_private *sp = netdev_priv(dev);
|
||||
|
@ -23,7 +23,7 @@
|
||||
|
||||
--- /dev/null
|
||||
+++ b/drivers/mtd/devices/ar2315.c
|
||||
@@ -0,0 +1,514 @@
|
||||
@@ -0,0 +1,515 @@
|
||||
+
|
||||
+/*
|
||||
+ * MTD driver for the SPI Flash Memory support on Atheros AR2315
|
||||
@ -114,10 +114,11 @@
|
||||
+};
|
||||
+
|
||||
+struct opcodes {
|
||||
+ __u16 code;
|
||||
+ __s8 tx_cnt;
|
||||
+ __s8 rx_cnt;
|
||||
+ __u16 code;
|
||||
+ __s8 tx_cnt;
|
||||
+ __s8 rx_cnt;
|
||||
+};
|
||||
+
|
||||
+const struct opcodes stm_opcodes[] = {
|
||||
+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
|
||||
+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
|
||||
|
@ -1,6 +1,6 @@
|
||||
--- /dev/null
|
||||
+++ b/drivers/watchdog/ar2315-wtd.c
|
||||
@@ -0,0 +1,199 @@
|
||||
@@ -0,0 +1,197 @@
|
||||
+/*
|
||||
+ * This program is free software; you can redistribute it and/or modify
|
||||
+ * it under the terms of the GNU General Public License as published by
|
||||
@ -106,26 +106,24 @@
|
||||
+ int ret = -ENOIOCTLCMD;
|
||||
+
|
||||
+ switch (cmd) {
|
||||
+ case WDIOC_GETSUPPORT:
|
||||
+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)) ? -EFAULT : 0;
|
||||
+ break;
|
||||
+
|
||||
+ case WDIOC_KEEPALIVE:
|
||||
+ ar2315_wdt_enable();
|
||||
+ ret = 0;
|
||||
+ break;
|
||||
+
|
||||
+ case WDIOC_SETTIMEOUT:
|
||||
+ ret = get_user(new_wdt_timeout, (int __user *)arg);
|
||||
+ if (ret)
|
||||
+ break;
|
||||
+ wdt_timeout = HEARTBEAT(new_wdt_timeout);
|
||||
+ ar2315_wdt_enable();
|
||||
+ break;
|
||||
+
|
||||
+ case WDIOC_GETTIMEOUT:
|
||||
+ ret = put_user(wdt_timeout, (int __user *)arg);
|
||||
+ case WDIOC_GETSUPPORT:
|
||||
+ ret = copy_to_user((void __user *)arg, &ident, sizeof(ident)) ?
|
||||
+ -EFAULT : 0;
|
||||
+ break;
|
||||
+ case WDIOC_KEEPALIVE:
|
||||
+ ar2315_wdt_enable();
|
||||
+ ret = 0;
|
||||
+ break;
|
||||
+ case WDIOC_SETTIMEOUT:
|
||||
+ ret = get_user(new_wdt_timeout, (int __user *)arg);
|
||||
+ if (ret)
|
||||
+ break;
|
||||
+ wdt_timeout = HEARTBEAT(new_wdt_timeout);
|
||||
+ ar2315_wdt_enable();
|
||||
+ break;
|
||||
+ case WDIOC_GETTIMEOUT:
|
||||
+ ret = put_user(wdt_timeout, (int __user *)arg);
|
||||
+ break;
|
||||
+ }
|
||||
+ return ret;
|
||||
+}
|
||||
|
@ -1,6 +1,6 @@
|
||||
--- a/drivers/net/ethernet/ar231x/ar231x.c
|
||||
+++ b/drivers/net/ethernet/ar231x/ar231x.c
|
||||
@@ -1273,7 +1273,7 @@ static int ar231x_mdiobus_probe (struct
|
||||
@@ -1272,7 +1272,7 @@ static int ar231x_mdiobus_probe (struct
|
||||
BUG_ON(!phydev);
|
||||
BUG_ON(phydev->attached_dev);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user