Update header file appropriately and disable read for ownership
Note that the FIQ support implements a workaround that provides a performance
boost over the traditional upstream workaround which ensures cache lines
are exclusive on driver CPU using 'read for ownership'.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
target/linux/cns3xxx/config-3.3 | 2 +-
target/linux/cns3xxx/patches-3.3/460-cns3xxx_fiq_support.patch | 9 ++++-----
2 files changed, 5 insertions(+), 6 deletions(-)
SVN-Revision: 33827
- properly check for the link up condition in the phylib adjust callback
- do not assign skb->dev, eth_type_trans() already does it
- handle skb allocation failures in the refill path
SVN-Revision: 33780
Commit r33248 introduced a regression by passing the board name plus
'board=' in the third argument. The board name string has to be put
into the image as identifier of the image type.
[juhosg: fix OpenMesh template instead of use of string substitution]
Signed-off-by: Marek Lindner <lindner_marek@yahoo.de>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 33767
Handle the different vlynq device versions, and make the vlynq code more
in line with the original vlynq implementation.
Patch from Daniel Gimpelevich.
SVN-Revision: 33755
At least devices without a switch present on the MDIO bus still get a valid
link and work as expected (such as the Linksys WAG54Gv2).
SVN-Revision: 33751
The Laguna boards do not use all the same pins for SDHCI as the Cavium
reference board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33684
The ARM11MPCore Timer/Watchdog registers start at offset 0x600 which is where
all mpcore-wdt boards point the driver base too. I believe this is wrong
because 0x600 is aliased to the timer/watchdog of the 'current CPU' where
0x700 is CPU0's timer/watchdog, and 0x800 is CPU1's timer/watchdog. Thus
if your timer/watchdog application is switching between CPU's it can end up
writing to the wrong CPU's registers which results in random board resets
from watchdog timeouts etc.
This patch forces the timer/watchdog driver to use CPU0's registers always.
Its my opinion that other mpcore-wdt boards should be doing the same thing.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33683
This allows sysupgrade for devices such as the Gateworks Avila/Cambria
product families based on the ixp4xx using the redboot bootloader with
combined FIS directory and RedBoot config partitions on larger FLASH
devices with larger eraseblocks.
This second iteration of this patch addresses previous issues:
- whitespace breakage fixed
- unlock in all scenarios
- simplification and fix logic bug
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33681
Enabling OPTIMIZE_FOR_SIZE cuts the kernel binary down by 50K which is
critical for some small-footprint boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33679
Several new features for newer boards:
- add additional UARTs present on some boards
- add additional LEDs present on some boards
- add HSS audio device codec present on some boards
- add support for GSC present on some boards
- add per model setup support for newer boards
- set FLASH window per-model for boards with larger FLASH
Some fixes:
- add IRQ mapping for additional PCI devices (USB Host)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
SVN-Revision: 33647
