Commit Graph

160 Commits

Author SHA1 Message Date
Martin Schiller
ddd1882811 lantiq/xrx200-net: add interrupt for second DMA TX channel to vr9.dtsi
Signed-off-by: Martin Schiller <mschiller@tdt.de>
2016-08-15 15:32:36 +02:00
Mathias Kresin
5947f7f85e lantiq: enable cpu temp driver for selected boards
According to the author of the cpu temp driver, not all xrx200 boards
have a cpu temperature sensor. For that reason enable the sensor only
for tested boards.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-08-10 02:04:31 +02:00
Mathias Kresin
91d5067091 lantiq: use the etop driver DT bindings only
Use the generic mtd-mac-address dts property to get a mac address from
flash instead of the lantiq specific one.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-08-10 02:04:31 +02:00
Mathias Kresin
1b7d6583a5 lantiq: fix mac address increments
Use the same mac address increment in device tree source file and
userspace.

Don't add a mac address increment to either the only mtd mac-address or
to all mac-addresses.

Fix a typo in the TDW89X0.dtsi file to add an increment.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-08-10 02:04:31 +02:00
Mathias Kresin
12fe4b5798 lantiq: use ath, eep-flash/mac-offset for ath eep nodes
No functional change, just easier to get what's the purpose of the hex
values.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-08-10 02:04:31 +02:00
Hauke Mehrtens
47cce1d5e4 lantiq: fix switch configuration for EASY80920
The device tree description misses some Ethernet ports and there was no
model specified for this board. In addition there was no switch
specific default configuration created.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2016-07-28 22:42:16 +02:00
Ben Mulvihill
1cc092f72b lantiq: mac address setting on BTHOMEHUBV3A
Rename uboot environment partition on BT Home Hub 3A so that mac address
setting works correctly.

Also, the mac address field in the ath9k calibration data is not used,
and should not be referenced in the dts.

Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>
2016-07-05 22:59:14 +02:00
Oswald Buddenhagen
9759fde40a lantiq: add support for ARV7506PW11 (Alice/O2 IAD 4421)
Ethernet, ADSL2+ and LEDs are fully functional.

Supporting the two TAE ports and SIP gateway was not attempted.

The WiFi is unreliable, due to experimental support for rt35xx family
devices by the rt2800pci driver.

Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
[rebase to LEDE HEAD]
[switch to normal image instead of brnboot image]
[remove not required pinmux child nodes keys, leds, ebu, exin, pci_in and pci_out]
[remove switch_rst pinmux child node (no support for hw reset in driver/setting a default GPIO value in DT]
[enable usage of the wireless LED]
[fixup mac address configuration]
Sgned-off-by: Mathias Kresin <dev@kresin.me>
2016-06-22 19:32:06 +02:00
Daniel Gimpelevich
34fdfbf328 lantiq: Slow down SPI flash on the DGN3500
The bootloader uses 30 MHz as the SPI frequency for flash on the Germany and
North America models, and 50 MHz for it on the worldwide model, but the Lantiq
SPI driver in OpenWrt and LEDE may access the flash differently such that
writes are capped at 20 MHz, leading to read errors reported on the worldwide
model at 30 MHz.

Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
Acked-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
2016-06-22 19:32:06 +02:00
John Crispin
f054e82bdc lantiq: remove gr7000 support
this seems to have never worked as the wrong SoC is selected

Signed-off-by: John Crispin <john@phrozen.org>
2016-06-22 19:32:06 +02:00
Hauke Mehrtens
84b3d92180 lantiq: make EASY80920 work with both chip versions
The EASY80920 is available with the A1X and the A2X chip version
depending on the board version. Add both firmware versions to device
tree and make the driver load the correct version depending on the chip
version.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2016-06-21 21:58:59 +02:00
Hauke Mehrtens
7f5b8cc376 lantiq: use new partition layout for EASY80920NAND
This matches the EASY80920NAND boards with UGW.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2016-06-21 21:58:59 +02:00
Mathias Kresin
153b3f05d4 lantiq: BTHOMEHUBV5A - use the power event code for the restart button
The restart event code is used in LEDE to trigger a factory reset on
long press as well.

By using the power event code, the restart functionality can be used
without being prone to trigger a factory reset.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-06-20 11:45:44 +02:00
John Crispin
d5666b98fa lantiq: fix fritz7320 wifi support
Signed-off-by: John Crispin <john@phrozen.org>
2016-06-14 06:43:02 +02:00
John Crispin
d57990e071 lantiq: fix ARV452CQW button gpio setup
Signed-off-by: John Crispin <john@phrozen.org>
2016-06-13 22:51:43 +02:00
John Crispin
bf007a480a lantiq: Add Support for Fritz!Box 7360 SL
Signed-off-by: Sebastian Ortwein <krone@animeland.de>
Tested-by: Guido Lipke <lipkegu@gmail.com>
2016-06-13 22:51:43 +02:00
John Crispin
b50b0cff2d lantiq: use new property name for eiu irqs
Signed-off-by: John Crispin <john@phrozen.org>
2016-06-13 22:51:41 +02:00
Felix Fietkau
2d48f93ff4 lantiq: add Buffalo WBMR-300HPD support
Signed-off-by: Felix Fietkau <nbd@nbd.name>
2016-06-11 09:49:13 +02:00
Daniel Gimpelevich
2b4e5d478b kernel: remove a hack that was obsoleted upstream
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
2016-05-27 16:08:47 +02:00
Daniel Gimpelevich
e8780b643b lantiq: Use the correct SPI flash speed for the Netgear DGN3500
Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
2016-05-27 16:08:47 +02:00
Mathias Kresin
db66b157db lantiq: VGV7510KW22 - enable the IP101A phy
The RJ45 WAN port is used for xDSL as well as the IP101A.

The pins 1,2,3,6 of the RJ45 are connected to the IP101A and the
pins 4,5 are connected to the xdsl chip.

Drop the ip101a-rst node. It can't be controlled and is not required
at all.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:17 +02:00
Mathias Kresin
4d5db712e3 lantiq: VGV7510KW22 - fix pinmux configuration
The STP pinmux was initially added in assumption LAN2 led is driven by
it. It worked somehow because STP group and gphy0 led0 share the GPIO.
Do it the right way by adding the gphy0 led0 the gphy function.

According to the author, the SPI node is a copy & paste leftover. Which
makes sense since nothing is connected to the SPI bus on this device.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:17 +02:00
Mathias Kresin
a9f7586ad2 lantiq: VGV7519 - fix brn partition layout
Use the brnboot partition layout as it is listed in the OpenWrt wiki
article for this board.

Configure the brnboot root selector for this device as well.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:17 +02:00
Mathias Kresin
28faa3f292 lantiq: VGV7519 - get mac address from board_config partition
Use the mac address stored in the board_config partition instead of a
static one.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:17 +02:00
Mathias Kresin
1e395608cc lantiq: VGV7519 - add vlan support
Add the lantiq,switch property to enable vlans and setup them up.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:16 +02:00
Mathias Kresin
1deab53d88 lantiq: VGV7519 - add second usb port
Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:16 +02:00
Mathias Kresin
79d92bb7ac lantiq: VGV7519 - cleanup pinmux configuration
Cleanup the pinmux configuration by removing the unused spi node. Nothing is connected to the SPI bus on devices.

The stp_out pinmux child node covers the same GPIOs as the already used
stp group.

The same applies to the gphy-leds_out pinmux node and the "gphy0
led1" as well as "gphy1 led0" groups.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:16 +02:00
Mathias Kresin
8a382f1221 lantiq: VGV7519 - remove/merge redundant parts in dts
Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-27 15:50:16 +02:00
John Crispin
a42e84b2db lantiq: fix regression in VG3503J.dts
9d0608eef3 - "lantiq: VG3503J - merge profiles"

resulted in the dts file missing the version string.

Signed-off-by: John Crispin <john@phrozen.org>
2016-05-24 17:17:36 +02:00
Mathias Kresin
abfdddfb3c lantiq: VG3503J - use the 11G firmware
Use the 11G firmware for the phys as the oem firmware does.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-23 11:03:25 +02:00
Mathias Kresin
9d0608eef3 lantiq: VG3503J - merge profiles
The only difference between the VG3503J profiles is the version of the
gphy firmware that gets loaded. This can be handled perfect fine in one
device tree source file.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2016-05-23 11:03:24 +02:00
blogic
d4de9f72f3 lantiq: VGV7510KW22BRN - set the phy clock source
VGV7510KW2 with VRX288 v1.2 has brnboot 1.8 installed. Starting with
this brnboot version, the "GPHY Clock Source" isn't set anymore by
brnboot, with the result that xrx200-net fails to probe/initialize the
phys.

Use the phy clock source device tree binding to specify the clock source.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49284
2016-05-10 10:43:12 +02:00
blogic
60ac485274 lantiq: VGV7510KW22BRN - support dual-image
Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49282
2016-05-10 10:43:12 +02:00
blogic
b7fc892eb5 lantiq: move partitions into partion table node
Starting with kernel 4.4, the use of partitions as direct subnodes of the
mtd device is discouraged and only supported for backward compatiblity
reasons.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49280
2016-05-10 10:43:12 +02:00
blogic
5ed2140162 lantiq: VG3503J - use the same PHY led functionality as the OEM firmware
Based on the vg3503j_gphy_led.sh script published in the VG3503J wiki
article, the OEM Firmware uses the following PHY led functionality:

    gphy led 0: LINK/ACTIVITY
    gphy led 1: LINK
    gphy led 2: ACTIVITY

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 49278
2016-05-10 10:43:12 +02:00
blogic
b529387d8c lantiq: use the same functionality for all ethernet phys led
The VGV7510KW22 has the leds for LAN1-3 connected to pin1 of the phys
and the led for LAN4 connect to pin0 of the phy. This results with the
current configuration in a fast flashing LAN4 led as soon as a network
cable is connected. Something similar was reported on the forum[1] for
the VGV7519 as well.

Since it isn't predicable to which pin a (single) phy led is connected,
use the (default) pin1 functionality

    Constant On: 10/100/1000MBit
    Blink Fast: None
    Blink Slow: None
    Pulse: TX/RX

for all ethernet phy leds.

After checking pictures of all vr9 boards, it looks like only the VG3503J
has more than one led connected per phy. Using the phy led device tree
bindings to assign the functionality to the "additional" leds, the
VG3503J phy leds should behave as before.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

[1] https://forum.openwrt.org/viewtopic.php?pid=321523

SVN-Revision: 49270
2016-05-10 10:43:12 +02:00
John Crispin
544efb9ad1 lantiq: remove read-only flag on two partitions on BTHOMEHUBV3A
Remove read-only flag on two partitions on BTHOMEHUBV3A:
  uboot-config - otherwise fw_setenv command cannot be used.
  ath9k-cal    - so that ath9k calibration data can be copied
                 to the partition on a newly installed board.

Signed-off-by: Ben Mulvihill <ben.mulvihill@gmail.com>

SVN-Revision: 49250
2016-04-26 11:44:03 +00:00
John Crispin
a0e8833cb5 lantiq: VGV7510KW22/VGV7519 update spi pinmux group
With the backport of the kernel 4.5 pinctrl-xway patches (3551609d &
826bca29) the pinmux group "spi" was splitted into "spi_di", "spi_do" &
"spi_clk". But the no longer existing group "spi" is still used by some
device tree source files.

This fixes the detection of the wireless chipset of the VGV7510KW22.

Signed-off-by: Mathias Kresin <openwrt@kresin.me>

SVN-Revision: 48658
2016-02-08 08:25:31 +00:00
John Crispin
7c0009a52e lantiq: BTHOMEHUBV5A - explicit select the flash device
The stock u-boot doesn't disable unused flash banks. Therefore, the nand
driver tries to initialize a not connected NOR flash and the device
hangs on boot.

Workaround the issue by selecting the second flash bank (NAND).

Signed-off-by: Mathias Kresin <openwrt@kresin.me>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48657
2016-02-08 08:25:22 +00:00
Felix Fietkau
6fd5449198 lantiq: Make the ar9.dtsi sram node match "simple-bus"
All other SoC types are using "lantiq,sram" and "simple-bus" to ensure
that all child nodes are set up correctly during linux kernel
initialization (plat_of_setup(void) in arch/mips/lantiq/prom.c). Without
this some of sram child nodes might not be parsed.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48548
2016-01-29 00:42:50 +00:00
Felix Fietkau
022855baf2 lantiq: Move the definition of the xrx200-net node to vr9.dtsi
This removes a lot of duplicate register and interrupt definitions by
moving the xrx200-net definition to vr9.dtsi and making all devices re-
use it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48547
2016-01-29 00:42:45 +00:00
Hauke Mehrtens
13b8b8c2e7 lantiq: add support for TP-Link VR200v
This adds basic support for TP-Link VR200v.
Currently the following parts are not working: FXO, Voice, DECT, WIFI (both)

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

SVN-Revision: 48328
2016-01-18 20:40:03 +00:00
Felix Fietkau
d64465556c lantiq: Remove incorrect PCIe compatible strings
Re-defining the compatible property is not required since the correct
value is inherited from vr9.dtsi.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48295
2016-01-17 19:56:16 +00:00
Felix Fietkau
04ad02d132 lantiq: Switch to the new SPI driver
Compared to the "old" driver:
- Each device must assign a pinctrl setting to the SPI node to allow the
  new SPI driver to configure the SPI pins.
  While here we are also using separate input and output settings so we
  are independent of whether the bootloader configures the pins correctly.
- We use the new "compatible" strings to make the driver choose the
  correct number of chip-selects for each SoC.
- The new driver starts counting the chip-selects at 1 (instead of 0, like
  the old one did). Thus we have to adjust the devices accordingly.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48293
2016-01-17 19:56:03 +00:00
Felix Fietkau
d5c5928d6b lantiq: Enable the hardware SPI driver on the DGN3500/DGN3500B
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48290
2016-01-17 19:55:42 +00:00
Felix Fietkau
d8b74320bd lantiq: Enable SPI for the EASY80920 board again
Also switch to the SPI definition provided by vr9.dtsi

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48289
2016-01-17 19:55:37 +00:00
Felix Fietkau
be8f9ad6f4 lantiq: Switch FRITZ3370 from spi-gpio to the hardware SPI driver
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48288
2016-01-17 19:55:31 +00:00
Felix Fietkau
9d558fb48e lantiq: Re-use the SPI node from vr9.dtsi in TDW89X0.dtsi
This removes the duplicate SPI register definition.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48287
2016-01-17 19:55:25 +00:00
Felix Fietkau
a5c177943b lantiq: Add the SPI node to ar9.dtsi and vr9.dtsi
This allows devices to use SPI without having to re-define (and thus
duplicating) the whole SPI node.
By default SPI is disabled (as before) because only few devices need it.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48286
2016-01-17 19:55:17 +00:00
Felix Fietkau
3f8a426056 lantiq: Configure the PCIe reset GPIO using OF
After the latest pinctrl backports there are only 50 (instead of 56 as
before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now
462, before it was 456). This means that any hardcoded GPIOs have to be
adjusted.
This broke the PCIe driver (which seems to be the only driver which uses
hardcoded GPIO numbers), it only reports:
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	pcie_rc_initialize link up failed!!!!!

To prevent more of these issues in the future we remove the hardcoded
PCIe reset GPIO definition and simply pass it via device-tree (like the
PCI driver does).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48285
2016-01-17 19:55:10 +00:00