02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
77 lines
2.3 KiB
Diff
77 lines
2.3 KiB
Diff
From 331294fa5c703536e27b79e9c112d162393f725a Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Thu, 26 Jun 2014 13:55:10 -0500
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Subject: [PATCH 178/182] dmaengine: qcom_adm: Add device tree binding
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Add device tree binding support for the QCOM ADM DMA driver.
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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Documentation/devicetree/bindings/dma/qcom_adm.txt | 60 ++++++++++++++++++++
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1 file changed, 60 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/dma/qcom_adm.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt
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@@ -0,0 +1,60 @@
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+QCOM ADM DMA Controller
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+
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+Required properties:
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+- compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960
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+- reg: Address range for DMA registers
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+- interrupts: Should contain one interrupt shared by all channels
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+- #dma-cells: must be <2>. First cell denotes the channel number. Second cell
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+ denotes CRCI (client rate control interface) flow control assignment.
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+- clocks: Should contain the core clock and interface clock.
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+- clock-names: Must contain "core" for the core clock and "iface" for the
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+ interface clock.
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+- resets: Must contain an entry for each entry in reset names.
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+- reset-names: Must include the following entries:
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+ - clk
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+ - c0
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+ - c1
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+ - c2
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+- qcom,ee: indicates the security domain identifier used in the secure world.
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+
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+Example:
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+ adm_dma: dma@18300000 {
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+ compatible = "qcom,adm";
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+ reg = <0x18300000 0x100000>;
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+ interrupts = <0 170 0>;
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+ #dma-cells = <2>;
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+
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+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
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+ clock-names = "core", "iface";
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+
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+ resets = <&gcc ADM0_RESET>,
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+ <&gcc ADM0_C0_RESET>,
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+ <&gcc ADM0_C1_RESET>,
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+ <&gcc ADM0_C2_RESET>;
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+ reset-names = "clk", "c0", "c1", "c2";
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+ qcom,ee = <0>;
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+ };
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+
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+DMA clients must use the format descripted in the dma.txt file, using a three
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+cell specifier for each channel.
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+
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+Each dmas request consists of 3 cells:
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+ 1. phandle pointing to the DMA controller
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+ 2. channel number
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+ 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0.
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+
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+Example:
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+
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+ spi4: spi@1a280000 {
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+ status = "ok";
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+ spi-max-frequency = <50000000>;
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+
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+ pinctrl-0 = <&spi_pins>;
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+ pinctrl-names = "default";
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+
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+ cs-gpios = <&qcom_pinmux 20 0>;
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+
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+ dmas = <&adm_dma 6 9>,
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+ <&adm_dma 5 10>;
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+ dma-names = "rx", "tx";
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+ };
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