174 lines
3.6 KiB
C
174 lines
3.6 KiB
C
#ifndef __IDT_DDR_H__
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#define __IDT_DDR_H__
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/*******************************************************************************
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*
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* Copyright 2002 Integrated Device Technology, Inc.
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* All rights reserved.
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*
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* DDR register definition.
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*
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* File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
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*
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* Author : ryan.holmQVist@idt.com
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* Date : 20011005
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* Update :
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* $Log: ddr.h,v $
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* Revision 1.2 2002/06/06 18:34:03 astichte
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* Added XXX_PhysicalAddress and XXX_VirtualAddress
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*
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* Revision 1.1 2002/05/29 17:33:21 sysarch
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* jba File moved from vcode/include/idt/acacia
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*
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*
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******************************************************************************/
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enum
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{
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DDR0_PhysicalAddress = 0x18018000,
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DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
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DDR0_VirtualAddress = 0xb8018000,
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DDR_VirtualAddress = DDR0_VirtualAddress, // Default
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} ;
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typedef struct DDR_s
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{
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u32 ddrbase ;
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u32 ddrmask ;
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u32 res1;
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u32 res2;
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u32 ddrc ;
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u32 ddrabase ;
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u32 ddramask ;
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u32 ddramap ;
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u32 ddrcust;
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u32 ddrrdc;
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u32 ddrspare;
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} volatile *DDR_t ;
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enum
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{
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DDR0BASE_baseaddr_b = 16,
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DDR0BASE_baseaddr_m = 0xffff0000,
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DDR0MASK_mask_b = 16,
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DDR0MASK_mask_m = 0xffff0000,
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DDR1BASE_baseaddr_b = 16,
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DDR1BASE_baseaddr_m = 0xffff0000,
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DDR1MASK_mask_b = 16,
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DDR1MASK_mask_m = 0xffff0000,
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DDRC_ata_b = 5,
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DDRC_ata_m = 0x000000E0,
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DDRC_dbw_b = 8,
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DDRC_dbw_m = 0x00000100,
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DDRC_wr_b = 9,
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DDRC_wr_m = 0x00000600,
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DDRC_ps_b = 11,
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DDRC_ps_m = 0x00001800,
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DDRC_dtype_b = 13,
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DDRC_dtype_m = 0x0000e000,
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DDRC_rfc_b = 16,
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DDRC_rfc_m = 0x000f0000,
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DDRC_rp_b = 20,
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DDRC_rp_m = 0x00300000,
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DDRC_ap_b = 22,
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DDRC_ap_m = 0x00400000,
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DDRC_rcd_b = 23,
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DDRC_rcd_m = 0x01800000,
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DDRC_cl_b = 25,
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DDRC_cl_m = 0x06000000,
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DDRC_dbm_b = 27,
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DDRC_dbm_m = 0x08000000,
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DDRC_sds_b = 28,
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DDRC_sds_m = 0x10000000,
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DDRC_atp_b = 29,
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DDRC_atp_m = 0x60000000,
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DDRC_re_b = 31,
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DDRC_re_m = 0x80000000,
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DDRRDC_ces_b = 0,
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DDRRDC_ces_m = 0x00000001,
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DDRRDC_ace_b = 1,
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DDRRDC_ace_m = 0x00000002,
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DDRABASE_baseaddr_b = 16,
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DDRABASE_baseaddr_m = 0xffff0000,
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DDRAMASK_mask_b = 16,
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DDRAMASK_mask_m = 0xffff0000,
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DDRAMAP_map_b = 16,
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DDRAMAP_map_m = 0xffff0000,
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DDRCUST_cs_b = 0,
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DDRCUST_cs_m = 0x00000003,
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DDRCUST_we_b = 2,
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DDRCUST_we_m = 0x00000004,
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DDRCUST_ras_b = 3,
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DDRCUST_ras_m = 0x00000008,
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DDRCUST_cas_b = 4,
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DDRCUST_cas_m = 0x00000010,
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DDRCUST_cke_b = 5,
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DDRCUST_cke_m = 0x00000020,
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DDRCUST_ba_b = 6,
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DDRCUST_ba_m = 0x000000c0,
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RCOUNT_rcount_b = 0,
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RCOUNT_rcount_m = 0x0000ffff,
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RCOMPARE_rcompare_b = 0,
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RCOMPARE_rcompare_m = 0x0000ffff,
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RTC_ce_b = 0,
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RTC_ce_m = 0x00000001,
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RTC_to_b = 1,
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RTC_to_m = 0x00000002,
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RTC_rqe_b = 2,
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RTC_rqe_m = 0x00000004,
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DDRDQSC_dm_b = 0,
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DDRDQSC_dm_m = 0x00000003,
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DDRDQSC_dqsbs_b = 2,
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DDRDQSC_dqsbs_m = 0x000000fc,
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DDRDQSC_db_b = 8,
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DDRDQSC_db_m = 0x00000100,
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DDRDQSC_dbsp_b = 9,
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DDRDQSC_dbsp_m = 0x01fffe00,
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DDRDQSC_bdp_b = 25,
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DDRDQSC_bdp_m = 0x7e000000,
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DDRDLLC_eao_b = 0,
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DDRDLLC_eao_m = 0x00000001,
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DDRDLLC_eo_b = 1,
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DDRDLLC_eo_m = 0x0000003e,
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DDRDLLC_fs_b = 6,
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DDRDLLC_fs_m = 0x000000c0,
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DDRDLLC_as_b = 8,
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DDRDLLC_as_m = 0x00000700,
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DDRDLLC_sp_b = 11,
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DDRDLLC_sp_m = 0x001ff800,
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DDRDLLFC_men_b = 0,
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DDRDLLFC_men_m = 0x00000001,
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DDRDLLFC_aen_b = 1,
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DDRDLLFC_aen_m = 0x00000002,
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DDRDLLFC_ff_b = 2,
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DDRDLLFC_ff_m = 0x00000004,
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DDRDLLTA_addr_b = 2,
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DDRDLLTA_addr_m = 0xfffffffc,
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DDRDLLED_dbe_b = 0,
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DDRDLLED_dbe_m = 0x00000001,
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DDRDLLED_dte_b = 1,
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DDRDLLED_dte_m = 0x00000002,
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} ;
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#endif // __IDT_DDR_H__
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