bc4f2c5ce4
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default DIV and REF_DIV values. Test on both AR7240, AR7241 and AR7242. Signed-off-by: Weijie Gao <hackpascal@gmail.com> SVN-Revision: 46856
23 lines
562 B
Diff
23 lines
562 B
Diff
--- a/arch/mips/ath79/clock.c
|
|
+++ b/arch/mips/ath79/clock.c
|
|
@@ -25,7 +25,7 @@
|
|
#include "common.h"
|
|
|
|
#define AR71XX_BASE_FREQ 40000000
|
|
-#define AR724X_BASE_FREQ 5000000
|
|
+#define AR724X_BASE_FREQ 40000000
|
|
#define AR913X_BASE_FREQ 5000000
|
|
|
|
struct clk {
|
|
@@ -99,8 +99,8 @@
|
|
div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
|
|
freq = div * ref_rate;
|
|
|
|
- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
|
|
- freq *= div;
|
|
+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
|
|
+ freq /= div;
|
|
|
|
cpu_rate = freq;
|
|
|