130 lines
4.0 KiB
Diff
130 lines
4.0 KiB
Diff
From bdc913d1ef5143a8728ae414fcb90f9ed87a58da Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Mon, 23 Dec 2013 00:32:39 -0300
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Subject: [PATCH] clk: sunxi: mod0 support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit implements support for the "module 0" type of clocks, as
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used by MMC, IR, NAND, SATA and other components.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Acked-by: Mike Turquette <mturquette@linaro.org>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 5 +-
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drivers/clk/sunxi/clk-sunxi.c | 57 +++++++++++++++++++++++
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2 files changed, 61 insertions(+), 1 deletion(-)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index 80b2a39..46d8433 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -35,10 +35,13 @@ Required properties:
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"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
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"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
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"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
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+ "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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-- clocks : shall be the input parent clock(s) phandle for the clock
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+- clocks : shall be the input parent clock(s) phandle for the clock. For
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+ multiplexed clocks, the list order must match the hardware
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+ programming order.
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- #clock-cells : from common clock binding; shall be set to 0 except for
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"allwinner,*-gates-clk" where it shall be set to 1
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index 649d7c3..af99b57 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -295,6 +295,47 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
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/**
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+ * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
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+ * MMC rate is calculated as follows
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+ * rate = (parent_rate >> p) / (m + 1);
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+ */
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+
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+static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div, calcm, calcp;
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+
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+ /* These clocks can only divide, so we will never be able to achieve
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+ * frequencies higher than the parent frequency */
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+ if (*freq > parent_rate)
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+ *freq = parent_rate;
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+
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+ div = parent_rate / *freq;
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+
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+ if (div < 16)
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+ calcp = 0;
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+ else if (div / 2 < 16)
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+ calcp = 1;
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+ else if (div / 4 < 16)
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+ calcp = 2;
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+ else
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+ calcp = 3;
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+
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+ calcm = DIV_ROUND_UP(div, 1 << calcp);
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+
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+ *freq = (parent_rate >> calcp) / calcm;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ *m = calcm - 1;
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+ *p = calcp;
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+}
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+
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+
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+
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+/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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@@ -341,6 +382,14 @@ struct factors_data {
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.pwidth = 2,
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};
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+/* user manual says "n" but it's really "p" */
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+static struct clk_factors_config sun4i_mod0_config = {
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+ .mshift = 0,
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+ .mwidth = 4,
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+ .pshift = 16,
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+ .pwidth = 2,
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+};
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+
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static const struct factors_data sun4i_pll1_data __initconst = {
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.enable = 31,
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.table = &sun4i_pll1_config,
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@@ -364,6 +413,13 @@ struct factors_data {
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.getter = sun4i_get_apb1_factors,
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};
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+static const struct factors_data sun4i_mod0_data __initconst = {
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+ .enable = 31,
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+ .mux = 24,
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+ .table = &sun4i_mod0_config,
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+ .getter = sun4i_get_mod0_factors,
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+};
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+
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static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
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const struct factors_data *data)
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{
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@@ -852,6 +908,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
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{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
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{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
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+ {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
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{}
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};
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--
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1.8.5.1
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