openwrt/target/linux
Felix Fietkau 3f8a426056 lantiq: Configure the PCIe reset GPIO using OF
After the latest pinctrl backports there are only 50 (instead of 56 as
before) GPIOs/pins exported (thus the first GPIO on VRX200 SoCs is now
462, before it was 456). This means that any hardcoded GPIOs have to be
adjusted.
This broke the PCIe driver (which seems to be the only driver which uses
hardcoded GPIO numbers), it only reports:
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	ifx_pcie_wait_phy_link_up timeout
	pcie_rc_initialize link up failed!!!!!

To prevent more of these issues in the future we remove the hardcoded
PCIe reset GPIO definition and simply pass it via device-tree (like the
PCI driver does).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

SVN-Revision: 48285
2016-01-17 19:55:10 +00:00
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adm5120
adm8668
ar7
ar71xx
arc770
arm64
at91
ath25
au1000
bcm53xx
brcm47xx
brcm63xx
brcm2708
cns3xxx
gemini
generic
imx6
ipq806x
ixp4xx
kirkwood
lantiq lantiq: Configure the PCIe reset GPIO using OF 2016-01-17 19:55:10 +00:00
malta
mcs814x
mediatek
mpc85xx
mvebu
mxs
netlogic
octeon
omap
omap24xx
orion
oxnas
ppc40x
ppc44x
ramips
rb532
realview
sunxi
uml
x86
xburst
Makefile