40 lines
1.5 KiB
Diff
40 lines
1.5 KiB
Diff
From 75ec90fda763b491e5169dcb6dce8abe3856d946 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Sat, 14 Dec 2013 20:58:57 +0100
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Subject: [PATCH] sun5i: Give PLL6 a sane initial value
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The upstream kernel does not override PLL values as set by power-on-reset
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and/or the bootloader if it can avoid doing so.
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The power-on-reset value for PLL6 is 2400MHz, which does not actually work,
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the kernel does not know this and 2400 / 48 is 50 MHz, so the kernel happily
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tries to use it as is for mmc.
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Set PLL6 to a working frequency so that the kernel can use it. This fixes
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mmc in the upstream kernel not working on sun5i.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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arch/arm/cpu/armv7/sunxi/clock.c | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
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index 57b136d..b9dd608 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock.c
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@@ -43,6 +43,11 @@ static void clock_init_safe(void)
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sdelay(200);
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writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
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CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
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+#ifdef CONFIG_SUN5I
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+ /* Power on reset default for PLL6 is 2400 MHz, which is faster then
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+ * it can reliable do :| Set it to a 600 MHz instead. */
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+ writel(0x21009900, &ccm->pll6_cfg);
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+#endif
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#ifdef CONFIG_SUN7I
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writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
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writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
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--
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1.8.5.1
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