566 lines
20 KiB
Diff
566 lines
20 KiB
Diff
--- /dev/null
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|
+++ b/arch/mips/include/asm/mach-lantiq/xway/irq.h
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@@ -0,0 +1,18 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifndef __LANTIQ_IRQ_H
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+#define __LANTIQ_IRQ_H
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+
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+#include <xway_irq.h>
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+
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+#define NR_IRQS 256
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+
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+#include_next <irq.h>
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
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@@ -0,0 +1,155 @@
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+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
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+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
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+
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+
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+/******************************************************************************
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+ Copyright (c) 2002, Infineon Technologies. All rights reserved.
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+
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+ No Warranty
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+ Because the program is licensed free of charge, there is no warranty for
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+ the program, to the extent permitted by applicable law. Except when
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+ otherwise stated in writing the copyright holders and/or other parties
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+ provide the program "as is" without warranty of any kind, either
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+ expressed or implied, including, but not limited to, the implied
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+ warranties of merchantability and fitness for a particular purpose. The
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+ entire risk as to the quality and performance of the program is with
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+ you. should the program prove defective, you assume the cost of all
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+ necessary servicing, repair or correction.
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+
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+ In no event unless required by applicable law or agreed to in writing
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+ will any copyright holder, or any other party who may modify and/or
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+ redistribute the program as permitted above, be liable to you for
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+ damages, including any general, special, incidental or consequential
|
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+ damages arising out of the use or inability to use the program
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+ (including but not limited to loss of data or data being rendered
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+ inaccurate or losses sustained by you or third parties or a failure of
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+ the program to operate with any other programs), even if such holder or
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+ other party has been advised of the possibility of such damages.
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+******************************************************************************/
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+
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+
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+/*
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+ * ####################################
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+ * Definition
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+ * ####################################
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+ */
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+
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+/*
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+ * Available Timer/Counter Index
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+ */
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+#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
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+#define TIMER_ANY 0x00
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+#define TIMER1A TIMER(1, 0)
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+#define TIMER1B TIMER(1, 1)
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+#define TIMER2A TIMER(2, 0)
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+#define TIMER2B TIMER(2, 1)
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+#define TIMER3A TIMER(3, 0)
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+#define TIMER3B TIMER(3, 1)
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+
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+/*
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+ * Flag of Timer/Counter
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+ * These flags specify the way in which timer is configured.
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+ */
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+/* Bit size of timer/counter. */
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+#define TIMER_FLAG_16BIT 0x0000
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+#define TIMER_FLAG_32BIT 0x0001
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+/* Switch between timer and counter. */
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+#define TIMER_FLAG_TIMER 0x0000
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+#define TIMER_FLAG_COUNTER 0x0002
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+/* Stop or continue when overflowing/underflowing. */
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+#define TIMER_FLAG_ONCE 0x0000
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+#define TIMER_FLAG_CYCLIC 0x0004
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+/* Count up or counter down. */
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+#define TIMER_FLAG_UP 0x0000
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+#define TIMER_FLAG_DOWN 0x0008
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+/* Count on specific level or edge. */
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+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
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+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
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+#define TIMER_FLAG_RISE_EDGE 0x0010
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+#define TIMER_FLAG_FALL_EDGE 0x0020
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+#define TIMER_FLAG_ANY_EDGE 0x0030
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+/* Signal is syncronous to module clock or not. */
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+#define TIMER_FLAG_UNSYNC 0x0000
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+#define TIMER_FLAG_SYNC 0x0080
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+/* Different interrupt handle type. */
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+#define TIMER_FLAG_NO_HANDLE 0x0000
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+#if defined(__KERNEL__)
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+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
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+#endif // defined(__KERNEL__)
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+#define TIMER_FLAG_SIGNAL 0x0300
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+/* Internal clock source or external clock source */
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+#define TIMER_FLAG_INT_SRC 0x0000
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+#define TIMER_FLAG_EXT_SRC 0x1000
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+
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+
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+/*
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+ * ioctl Command
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+ */
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+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
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+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
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+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
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+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
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+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
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+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
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+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
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+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
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+
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+/*
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+ * Data Type Used to Call ioctl
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+ */
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+struct gptu_ioctl_param {
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+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
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+ * GPTU_SET_COUNTER, this field is ID of expected *
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+ * timer/counter. If it's zero, a timer/counter would *
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+ * be dynamically allocated and ID would be stored in *
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+ * this field. *
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+ * In command GPTU_GET_COUNT_VALUE, this field is *
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+ * ignored. *
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+ * In other command, this field is ID of timer/counter *
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+ * allocated. */
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+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
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+ * GPTU_SET_COUNTER, this field contains flags to *
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+ * specify how to configure timer/counter. *
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+ * In command GPTU_START_TIMER, zero indicate start *
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+ * and non-zero indicate resume timer/counter. *
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+ * In other command, this field is ignored. */
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+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
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+ * init/reload value. *
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+ * In command GPTU_SET_TIMER, this field contains *
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+ * frequency (0.001Hz) of timer. *
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+ * In command GPTU_GET_COUNT_VALUE, current count *
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+ * value would be stored in this field. *
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+ * In command GPTU_CALCULATE_DIVIDER, this field *
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+ * contains frequency wanted, and after calculation, *
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+ * divider would be stored in this field to overwrite *
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+ * the frequency. *
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+ * In other command, this field is ignored. */
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+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
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+ * if signal is required, this field contains process *
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+ * ID to which signal would be sent. *
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+ * In other command, this field is ignored. */
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+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
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+ * if signal is required, this field contains signal *
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+ * number which would be sent. *
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+ * In other command, this field is ignored. */
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+};
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+
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+/*
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+ * ####################################
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+ * Data Type
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+ * ####################################
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+ */
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+typedef void (*timer_callback)(unsigned long arg);
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+
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+extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
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+extern int ifxmips_free_timer(unsigned int);
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+extern int ifxmips_start_timer(unsigned int, int);
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+extern int ifxmips_stop_timer(unsigned int);
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+extern int ifxmips_reset_counter_flags(u32 timer, u32 flags);
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+extern int ifxmips_get_count_value(unsigned int, unsigned long *);
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+extern u32 ifxmips_cal_divider(unsigned long);
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+extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
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+extern int ifxmips_set_counter(unsigned int timer, unsigned int flag,
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+ u32 reload, unsigned long arg1, unsigned long arg2);
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+
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+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/xway/xway.h
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@@ -0,0 +1,121 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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|
+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2005 infineon
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifdef CONFIG_SOC_LANTIQ_XWAY
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+
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+#ifndef _LQ_XWAY_H__
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+#define _LQ_XWAY_H__
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+
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+#include <lantiq.h>
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+
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+/* request a non-gpio and set the PIO config */
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+extern int lq_gpio_request(unsigned int pin, unsigned int alt0,
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+ unsigned int alt1, unsigned int dir, const char *name);
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+extern int lq_gpio_setconfig(unsigned int pin, unsigned int reg, unsigned int val);
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+
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+extern void lq_pmu_enable(unsigned int module);
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+extern void lq_pmu_disable(unsigned int module);
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+
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+extern unsigned int lq_get_fpi_bus_clock(int bus);
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+
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+#define BOARD_SYSTEM_TYPE "LANTIQ"
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+
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+/*------------ Chip IDs */
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+#define SOC_ID_DANUBE1 0x129
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+#define SOC_ID_DANUBE2 0x12B
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+#define SOC_ID_TWINPASS 0x12D
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+#define SOC_ID_ARX188 0x16C
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+#define SOC_ID_ARX168 0x16D
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+#define SOC_ID_ARX182 0x16F
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+
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+/*------------ SoC Types */
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+#define SOC_TYPE_DANUBE 0x01
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+#define SOC_TYPE_TWINPASS 0x02
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+#define SOC_TYPE_AR9 0x03
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+
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+/*------------ ASC0/1 */
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+#define LQ_ASC0_BASE 0x1E100400
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+#define LQ_ASC1_BASE 0x1E100C00
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+#define LQ_ASC_SIZE 0x400
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+
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+/*------------ RCU */
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+#define LQ_RCU_BASE_ADDR 0xBF203000
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+
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+/*------------ GPTU */
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+#define LQ_GPTU_BASE_ADDR 0xB8000300
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+
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+/*------------ EBU */
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+#define LQ_EBU_GPIO_START 0x14000000
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+#define LQ_EBU_GPIO_SIZE 0x1000
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+
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+#define LQ_EBU_BASE_ADDR 0xBE105300
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+
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+#define LQ_EBU_BUSCON0 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0060))
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+#define LQ_EBU_PCC_CON ((u32 *)(LQ_EBU_BASE_ADDR + 0x0090))
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+#define LQ_EBU_PCC_IEN ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A4))
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+#define LQ_EBU_PCC_ISTAT ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A0))
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+#define LQ_EBU_BUSCON1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0064))
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+#define LQ_EBU_ADDRSEL1 ((u32 *)(LQ_EBU_BASE_ADDR + 0x0024))
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+
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+#define EBU_WRDIS 0x80000000
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+
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+/*------------ CGU */
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+#define LQ_CGU_BASE_ADDR (KSEG1 + 0x1F103000)
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+
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+/*------------ PMU */
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+#define LQ_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
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+
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+#define PMU_DMA 0x0020
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+#define PMU_USB 0x8041
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+#define PMU_LED 0x0800
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+#define PMU_GPT 0x1000
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+#define PMU_PPE 0x2000
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+#define PMU_FPI 0x4000
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+#define PMU_SWITCH 0x10000000
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+
|
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+/*------------ ETOP */
|
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+#define LQ_PPE32_BASE_ADDR 0xBE180000
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+#define LQ_PPE32_SIZE 0x40000
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+
|
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+/*------------ DMA */
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+#define LQ_DMA_BASE_ADDR 0xBE104100
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+
|
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+/*------------ PCI */
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+#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
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+#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
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+
|
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+/*------------ WDT */
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+#define LQ_WDT_BASE 0x1F880000
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+#define LQ_WDT_SIZE 0x400
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+
|
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+/*------------ Serial To Parallel conversion */
|
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+#define LQ_STP_BASE 0x1E100BB0
|
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+#define LQ_STP_SIZE 0x40
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+
|
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+/*------------ GPIO */
|
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+#define LQ_GPIO0_BASE_ADDR 0x1E100B10
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+#define LQ_GPIO1_BASE_ADDR 0x1E100B40
|
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+#define LQ_GPIO_SIZE 0x30
|
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+
|
|
+/*------------ SSC */
|
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+#define LQ_SSC_BASE_ADDR (KSEG1 + 0x1e100800)
|
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+
|
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+/*------------ MEI */
|
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+#define LQ_MEI_BASE_ADDR (KSEG1 + 0x1E116000)
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+
|
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+/*------------ DEU */
|
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+#define LQ_DEU_BASE (KSEG1 + 0x1E103100)
|
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+
|
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+/*------------ MPS */
|
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+#define LQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
|
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+#define LQ_MPS_CHIPID ((u32 *)(LQ_MPS_BASE_ADDR + 0x0344))
|
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+
|
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+#endif
|
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+
|
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+#endif
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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@@ -0,0 +1,194 @@
|
|
+/*
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
|
+ * by the Free Software Foundation.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
|
|
+ *
|
|
+ * Copyright (C) 2005 infineon
|
|
+ * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
|
|
+ *
|
|
+ */
|
|
+#ifndef _LQ_DMA_H__
|
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+#define _LQ_DMA_H__
|
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+
|
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+#define RCV_INT 1
|
|
+#define TX_BUF_FULL_INT 2
|
|
+#define TRANSMIT_CPT_INT 4
|
|
+#define LQ_DMA_CH_ON 1
|
|
+#define LQ_DMA_CH_OFF 0
|
|
+#define LQ_DMA_CH_DEFAULT_WEIGHT 100
|
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+
|
|
+enum attr_t{
|
|
+ TX = 0,
|
|
+ RX = 1,
|
|
+ RESERVED = 2,
|
|
+ DEFAULT = 3,
|
|
+};
|
|
+
|
|
+#define DMA_OWN 1
|
|
+#define CPU_OWN 0
|
|
+#define DMA_MAJOR 250
|
|
+
|
|
+#define DMA_DESC_OWN_CPU 0x0
|
|
+#define DMA_DESC_OWN_DMA 0x80000000
|
|
+#define DMA_DESC_CPT_SET 0x40000000
|
|
+#define DMA_DESC_SOP_SET 0x20000000
|
|
+#define DMA_DESC_EOP_SET 0x10000000
|
|
+
|
|
+#define MISCFG_MASK 0x40
|
|
+#define RDERR_MASK 0x20
|
|
+#define CHOFF_MASK 0x10
|
|
+#define DESCPT_MASK 0x8
|
|
+#define DUR_MASK 0x4
|
|
+#define EOP_MASK 0x2
|
|
+
|
|
+#define DMA_DROP_MASK (1<<31)
|
|
+
|
|
+#define LQ_DMA_RX -1
|
|
+#define LQ_DMA_TX 1
|
|
+
|
|
+struct dma_chan_map {
|
|
+ const char *dev_name;
|
|
+ enum attr_t dir;
|
|
+ int pri;
|
|
+ int irq;
|
|
+ int rel_chan_no;
|
|
+};
|
|
+
|
|
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
|
|
+struct rx_desc {
|
|
+ u32 data_length:16;
|
|
+ volatile u32 reserved:7;
|
|
+ volatile u32 byte_offset:2;
|
|
+ volatile u32 Burst_length_offset:3;
|
|
+ volatile u32 EoP:1;
|
|
+ volatile u32 Res:1;
|
|
+ volatile u32 C:1;
|
|
+ volatile u32 OWN:1;
|
|
+ volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
|
|
+};
|
|
+
|
|
+struct tx_desc {
|
|
+ volatile u32 data_length:16;
|
|
+ volatile u32 reserved1:7;
|
|
+ volatile u32 byte_offset:5;
|
|
+ volatile u32 EoP:1;
|
|
+ volatile u32 SoP:1;
|
|
+ volatile u32 C:1;
|
|
+ volatile u32 OWN:1;
|
|
+ volatile u32 Data_Pointer; /* fixme: should be 28 bits here */
|
|
+};
|
|
+#else /* BIG */
|
|
+struct rx_desc {
|
|
+ union {
|
|
+ struct {
|
|
+ volatile u32 OWN:1;
|
|
+ volatile u32 C:1;
|
|
+ volatile u32 SoP:1;
|
|
+ volatile u32 EoP:1;
|
|
+ volatile u32 Burst_length_offset:3;
|
|
+ volatile u32 byte_offset:2;
|
|
+ volatile u32 reserve:7;
|
|
+ volatile u32 data_length:16;
|
|
+ } field;
|
|
+ volatile u32 word;
|
|
+ } status;
|
|
+ volatile u32 Data_Pointer;
|
|
+};
|
|
+
|
|
+struct tx_desc {
|
|
+ union {
|
|
+ struct {
|
|
+ volatile u32 OWN:1;
|
|
+ volatile u32 C:1;
|
|
+ volatile u32 SoP:1;
|
|
+ volatile u32 EoP:1;
|
|
+ volatile u32 byte_offset:5;
|
|
+ volatile u32 reserved:7;
|
|
+ volatile u32 data_length:16;
|
|
+ } field;
|
|
+ volatile u32 word;
|
|
+ } status;
|
|
+ volatile u32 Data_Pointer;
|
|
+};
|
|
+#endif /* ENDIAN */
|
|
+
|
|
+struct dma_channel_info {
|
|
+ /* relative channel number */
|
|
+ int rel_chan_no;
|
|
+ /* class for this channel for QoS */
|
|
+ int pri;
|
|
+ /* specify byte_offset */
|
|
+ int byte_offset;
|
|
+ /* direction */
|
|
+ int dir;
|
|
+ /* irq number */
|
|
+ int irq;
|
|
+ /* descriptor parameter */
|
|
+ int desc_base;
|
|
+ int desc_len;
|
|
+ int curr_desc;
|
|
+ int prev_desc; /* only used if it is a tx channel*/
|
|
+ /* weight setting for WFQ algorithm*/
|
|
+ int weight;
|
|
+ int default_weight;
|
|
+ int packet_size;
|
|
+ int burst_len;
|
|
+ /* on or off of this channel */
|
|
+ int control;
|
|
+ /* optional information for the upper layer devices */
|
|
+#if defined(CONFIG_LQ_ETHERNET_D2) || defined(CONFIG_LQ_PPA)
|
|
+ void *opt[64];
|
|
+#else
|
|
+ void *opt[25];
|
|
+#endif
|
|
+ /* Pointer to the peripheral device who is using this channel */
|
|
+ void *dma_dev;
|
|
+ /* channel operations */
|
|
+ void (*open)(struct dma_channel_info *pCh);
|
|
+ void (*close)(struct dma_channel_info *pCh);
|
|
+ void (*reset)(struct dma_channel_info *pCh);
|
|
+ void (*enable_irq)(struct dma_channel_info *pCh);
|
|
+ void (*disable_irq)(struct dma_channel_info *pCh);
|
|
+};
|
|
+
|
|
+struct dma_device_info {
|
|
+ /* device name of this peripheral */
|
|
+ char device_name[15];
|
|
+ int reserved;
|
|
+ int tx_burst_len;
|
|
+ int rx_burst_len;
|
|
+ int default_weight;
|
|
+ int current_tx_chan;
|
|
+ int current_rx_chan;
|
|
+ int num_tx_chan;
|
|
+ int num_rx_chan;
|
|
+ int max_rx_chan_num;
|
|
+ int max_tx_chan_num;
|
|
+ struct dma_channel_info *tx_chan[20];
|
|
+ struct dma_channel_info *rx_chan[20];
|
|
+ /*functions, optional*/
|
|
+ u8 *(*buffer_alloc)(int len, int *offset, void **opt);
|
|
+ void (*buffer_free)(u8 *dataptr, void *opt);
|
|
+ int (*intr_handler)(struct dma_device_info *info, int status);
|
|
+ void *priv; /* used by peripheral driver only */
|
|
+};
|
|
+
|
|
+struct dma_device_info *dma_device_reserve(char *dev_name);
|
|
+void dma_device_release(struct dma_device_info *dev);
|
|
+void dma_device_register(struct dma_device_info *info);
|
|
+void dma_device_unregister(struct dma_device_info *info);
|
|
+int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt);
|
|
+int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len,
|
|
+ void *opt);
|
|
+
|
|
+#endif
|
|
+
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_irq.h
|
|
@@ -0,0 +1,62 @@
|
|
+/*
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
|
+ * by the Free Software Foundation.
|
|
+ *
|
|
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
|
+ */
|
|
+
|
|
+#ifndef _LANTIQ_XWAY_IRQ_H__
|
|
+#define _LANTIQ_XWAY_IRQ_H__
|
|
+
|
|
+#define INT_NUM_IRQ0 8
|
|
+#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
|
|
+#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
|
|
+#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
|
|
+#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
|
|
+#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
|
|
+#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
|
|
+
|
|
+#define LQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7))
|
|
+#define LQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2)
|
|
+#define LQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3)
|
|
+
|
|
+#define LQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
|
|
+#define LQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
|
|
+#define LQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
|
|
+
|
|
+#define LQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
|
|
+#define LQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
|
|
+
|
|
+#define LQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
|
|
+#define LQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
|
|
+#define LQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
|
|
+
|
|
+#define MIPS_CPU_TIMER_IRQ 7
|
|
+
|
|
+#define LQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
|
|
+#define LQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
|
|
+#define LQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
|
|
+#define LQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
|
|
+#define LQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
|
|
+#define LQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
|
|
+#define LQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
|
|
+#define LQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
|
|
+#define LQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
|
|
+#define LQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
|
|
+#define LQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
|
|
+#define LQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
|
|
+#define LQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
|
|
+#define LQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
|
|
+#define LQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
|
|
+#define LQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
|
|
+#define LQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
|
|
+#define LQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
|
|
+#define LQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
|
|
+#define LQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
|
|
+
|
|
+#define LQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
|
|
+
|
|
+#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
|
|
+
|
|
+#endif
|