336 lines
8.0 KiB
Diff
336 lines
8.0 KiB
Diff
--- /dev/null
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+++ b/arch/arm/plat-fa/gpio.c
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@@ -0,0 +1,275 @@
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+/*
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+ * Gpiochip and interrupt routines for Faraday FA526 based SoCs
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+ *
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+ * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
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+ * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * Based on plat-mxc/gpio.c:
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+ * MXC GPIO supchip. (c) 2008 Daniel Mack <daniel@caiaq.de>
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+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+#include <linux/spinlock.h>
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+
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+#include <plat/gpio.h>
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+
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+#define GPIO_DATA_OUT 0x0
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+#define GPIO_DATA_IN 0x4
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+#define GPIO_DIR 0x8
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+#define GPIO_DATA_SET 0x10
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+#define GPIO_DATA_CLR 0x14
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+#define GPIO_PULL_EN 0x18
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+#define GPIO_PULL_TYPE 0x1C
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+#define GPIO_INT_EN 0x20
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+#define GPIO_INT_STAT 0x24
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+#define GPIO_INT_MASK 0x2C
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+#define GPIO_INT_CLR 0x30
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+#define GPIO_INT_TYPE 0x34
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+#define GPIO_INT_BOTH_EDGE 0x38
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+#define GPIO_INT_LEVEL 0x3C
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+#define GPIO_DEBOUNCE_EN 0x40
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+#define GPIO_DEBOUNCE_PRESCALE 0x44
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+
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+#define GPIO_REGS_SIZE 0x48
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+
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+static DEFINE_SPINLOCK(fa_gpio_lock);
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+
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+static inline struct fa_gpio_chip *to_fgc(struct gpio_chip *chip)
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+{
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+ return container_of(chip, struct fa_gpio_chip, gpio_chip);
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+}
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+
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+static void _fa_gpio_irq_setenable(unsigned int irq, int enable)
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+{
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+ struct fa_gpio_chip *fgc = get_irq_chip_data(irq);
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+ void __iomem *base = fgc->mem_base;
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+ unsigned int gpio = irq - fgc->irq_base;
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+ unsigned int reg;
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+
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+ reg = __raw_readl(base + GPIO_INT_EN);
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+ reg = (reg & (~(1 << gpio))) | (!!enable << gpio);
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+ __raw_writel(reg, base + GPIO_INT_EN);
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+}
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+
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+static void fa_gpio_irq_ack(unsigned int irq)
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+{
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+ struct fa_gpio_chip *fgc = get_irq_chip_data(irq);
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+ unsigned int gpio = irq - fgc->irq_base;
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+
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+ __raw_writel(1 << gpio, fgc->mem_base + GPIO_INT_CLR);
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+}
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+
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+static void fa_gpio_irq_mask(unsigned int irq)
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+{
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+ _fa_gpio_irq_setenable(irq, 0);
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+}
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+
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+static void fa_gpio_irq_unmask(unsigned int irq)
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+{
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+ _fa_gpio_irq_setenable(irq, 1);
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+}
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+
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+static int fa_gpio_irq_set_type(unsigned int irq, unsigned int type)
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+{
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+ struct fa_gpio_chip *fgc = get_irq_chip_data(irq);
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+ void __iomem *base = fgc->mem_base;
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+ unsigned int gpio = irq - fgc->irq_base;
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+ unsigned int gpio_mask = 1 << gpio;
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+ unsigned int reg_both, reg_level, reg_type;
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+
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+ reg_type = __raw_readl(base + GPIO_INT_TYPE);
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+ reg_level = __raw_readl(base + GPIO_INT_LEVEL);
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+ reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
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+
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+ switch (type) {
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+ case IRQ_TYPE_EDGE_BOTH:
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+ reg_type &= ~gpio_mask;
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+ reg_both |= gpio_mask;
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+ break;
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+ case IRQ_TYPE_EDGE_RISING:
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+ reg_type &= ~gpio_mask;
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+ reg_both &= ~gpio_mask;
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+ reg_level &= ~gpio_mask;
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+ break;
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+ case IRQ_TYPE_EDGE_FALLING:
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+ reg_type &= ~gpio_mask;
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+ reg_both &= ~gpio_mask;
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+ reg_level |= gpio_mask;
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+ break;
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+ case IRQ_TYPE_LEVEL_HIGH:
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+ reg_type |= gpio_mask;
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+ reg_level &= ~gpio_mask;
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+ break;
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+ case IRQ_TYPE_LEVEL_LOW:
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+ reg_type |= gpio_mask;
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+ reg_level |= gpio_mask;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ __raw_writel(reg_type, base + GPIO_INT_TYPE);
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+ __raw_writel(reg_level, base + GPIO_INT_LEVEL);
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+ __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
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+
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+ fa_gpio_irq_ack(irq);
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+
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+ return 0;
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+}
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+
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+static void fa_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ struct fa_gpio_data *data = get_irq_data(irq);
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+ unsigned int chip;
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+
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+ for (chip = 0; chip < data->nchips; chip++) {
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+ struct fa_gpio_chip *fgc = &data->chips[chip];
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+ unsigned int status;
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+ unsigned int i;
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+
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+ status = __raw_readl(fgc->mem_base + GPIO_INT_STAT);
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+ for (i = fgc->irq_base; status != 0; status >>= 1, i++) {
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+ if ((status & 1) == 0)
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+ continue;
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+
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+ BUG_ON(!(irq_desc[i].handle_irq));
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+ irq_desc[i].handle_irq(i, &irq_desc[i]);
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+ }
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+ }
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+}
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+
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+static struct irq_chip fa_gpio_irq_chip = {
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+ .name = "GPIO",
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+ .ack = fa_gpio_irq_ack,
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+ .mask = fa_gpio_irq_mask,
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+ .unmask = fa_gpio_irq_unmask,
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+ .set_type = fa_gpio_irq_set_type,
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+};
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+
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+static void _fa_gpio_set_direction(struct fa_gpio_chip *fgc, unsigned offset,
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+ int is_output)
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+{
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+ unsigned int reg;
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+
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+ reg = __raw_readl(fgc->mem_base + GPIO_DIR);
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+ if (is_output)
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+ reg |= 1 << offset;
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+ else
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+ reg &= ~(1 << offset);
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+ __raw_writel(reg, fgc->mem_base + GPIO_DIR);
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+}
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+
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+static void _fa_gpio_set(struct fa_gpio_chip *fgc, unsigned offset, int value)
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+{
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+ if (value)
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+ __raw_writel(1 << offset, fgc->mem_base + GPIO_DATA_SET);
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+ else
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+ __raw_writel(1 << offset, fgc->mem_base + GPIO_DATA_CLR);
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+}
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+
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+static void fa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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+{
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+ struct fa_gpio_chip *fgc = to_fgc(chip);
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+
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+ _fa_gpio_set(fgc, offset, value);
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+}
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+
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+static int fa_gpio_get(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct fa_gpio_chip *fgc = to_fgc(chip);
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+
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+ return (__raw_readl(fgc->mem_base + GPIO_DATA_IN) >> offset) & 1;
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+}
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+
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+static int fa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct fa_gpio_chip *fgc = to_fgc(chip);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&fa_gpio_lock, flags);
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+
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+ _fa_gpio_set_direction(fgc, offset, 0);
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+
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+ spin_unlock_irqrestore(&fa_gpio_lock, flags);
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+
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+ return 0;
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+}
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+
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+static int fa_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned offset,
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+ int value)
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+{
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+ struct fa_gpio_chip *fgc = to_fgc(chip);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&fa_gpio_lock, flags);
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+
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+ _fa_gpio_set(fgc, offset, value);
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+ _fa_gpio_set_direction(fgc, offset, 1);
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+
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+ spin_unlock_irqrestore(&fa_gpio_lock, flags);
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+
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+ return 0;
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+}
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+
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+static int fa_gpio_init_chip(struct fa_gpio_chip *fgc)
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+{
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+ void __iomem *mem_base;
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+ unsigned int i;
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+ int err;
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+
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+ mem_base = ioremap(fgc->map_base, GPIO_REGS_SIZE);
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+ if (!mem_base)
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+ return -ENXIO;
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+
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+ fgc->mem_base = mem_base;
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+
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+ fgc->gpio_chip.direction_input = fa_gpio_direction_input;
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+ fgc->gpio_chip.direction_output = fa_gpio_direction_output;
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+ fgc->gpio_chip.get = fa_gpio_get;
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+ fgc->gpio_chip.set = fa_gpio_set;
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+
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+ /* disable, unmask and clear all interrupts */
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+ __raw_writel(0x0, mem_base + GPIO_INT_EN);
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+ __raw_writel(0x0, mem_base + GPIO_INT_MASK);
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+ __raw_writel(~0x0, mem_base + GPIO_INT_CLR);
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+
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+ for (i = fgc->irq_base;
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+ i < fgc->irq_base + fgc->gpio_chip.ngpio; i++) {
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+ set_irq_chip(i, &fa_gpio_irq_chip);
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+ set_irq_chip_data(i, fgc);
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+ set_irq_handler(i, handle_edge_irq);
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+ set_irq_flags(i, IRQF_VALID);
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+ }
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+
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+ err = gpiochip_add(&fgc->gpio_chip);
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+ if (err)
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+ goto unmap;
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+
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+ return 0;
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+
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+ unmap:
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+ iounmap(fgc->mem_base);
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+ return err;
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+}
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+
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+void __init fa_gpio_init(struct fa_gpio_data *data)
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+{
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+ unsigned int i;
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+
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+ for (i = 0; i < data->nchips; i++) {
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+ int err;
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+
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+ err = fa_gpio_init_chip(&data->chips[i]);
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+ if (WARN(err, "GPIO init failed\n"))
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+ return;
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+ }
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+
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+ set_irq_chained_handler(data->irq, fa_gpio_irq_handler);
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+ set_irq_data(data->irq, data);
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+}
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--- /dev/null
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+++ b/arch/arm/plat-fa/include/plat/gpio.h
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@@ -0,0 +1,33 @@
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+/*
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+ * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * This file is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License, Version 2, as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#ifndef _FA_GPIO_H
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+#define _FA_GPIO_H
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+
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+#include <linux/init.h>
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+#include <linux/gpio.h>
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+#include <linux/irq.h>
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+#include <linux/io.h>
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+
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+struct fa_gpio_chip {
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+ struct gpio_chip gpio_chip;
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+ unsigned int map_base;
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+ unsigned int irq_base;
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+
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+ void __iomem *mem_base;
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+};
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+
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+struct fa_gpio_data {
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+ struct fa_gpio_chip *chips;
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+ unsigned int nchips;
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+ unsigned int irq;
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+};
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+
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+void __init fa_gpio_init(struct fa_gpio_data *data);
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+
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+#endif /* _FA_GPIO_H */
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--- a/arch/arm/plat-fa/Kconfig
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+++ b/arch/arm/plat-fa/Kconfig
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@@ -1,5 +1,8 @@
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if PLAT_FA
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+config PLAT_FA_GPIO
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+ def_bool n
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+
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config PLAT_FA_TIME
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def_bool n
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--- a/arch/arm/plat-fa/Makefile
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+++ b/arch/arm/plat-fa/Makefile
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@@ -4,6 +4,7 @@
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obj-y :=
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+obj-$(CONFIG_PLAT_FA_GPIO) += gpio.o
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obj-$(CONFIG_PLAT_FA_TIME) += time.o
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obj-m :=
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