c9ae111a20
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13. This work mainly covers: * Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family, and the Armada family. * timer initialization update, and access function for the Armada family. * Generic IRQ handling backporting. * Some bug fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39566
68 lines
2.4 KiB
Diff
68 lines
2.4 KiB
Diff
From c312e183e96bed3b727888673d4b6b54b8e6283e Mon Sep 17 00:00:00 2001
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From: Brian Norris <computersforpeace@gmail.com>
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Date: Thu, 14 Nov 2013 14:41:32 -0800
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Subject: [PATCH 154/203] mtd: nand: pxa3xx: make ECC configuration checks more
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explicit
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The Armada BCH configuration in this driver uses one of the two
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following ECC schemes:
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16-bit correction per 2048 bytes
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16-bit correction per 1024 bytes
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These are sufficient for mapping to the 4-bit per 512-bytes and 8-bit
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per 512-bytes (respectively) minimum correctability requirements of many
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common NAND.
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The current code only checks for the required strength (4-bit or 8-bit)
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without checking the ECC step size that is associated with that strength
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(and simply assumes it is 512). While that is often a safe assumption to
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make, let's make it explicit, since we have that information.
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Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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Tested-by: Daniel Mack <zonque@gmail.com>
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---
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drivers/mtd/nand/pxa3xx_nand.c | 15 ++++++++++++---
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1 file changed, 12 insertions(+), 3 deletions(-)
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--- a/drivers/mtd/nand/pxa3xx_nand.c
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+++ b/drivers/mtd/nand/pxa3xx_nand.c
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@@ -1364,9 +1364,13 @@ static int pxa_ecc_init(struct pxa3xx_na
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static int armada370_ecc_init(struct pxa3xx_nand_info *info,
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struct nand_ecc_ctrl *ecc,
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- int strength, int page_size)
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+ int strength, int ecc_stepsize, int page_size)
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{
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- if (strength == 4 && page_size == 4096) {
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+ /*
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+ * Required ECC: 4-bit correction per 512 bytes
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+ * Select: 16-bit correction per 2048 bytes
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+ */
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+ if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
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info->ecc_bch = 1;
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info->chunk_size = 2048;
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info->spare_size = 32;
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@@ -1377,7 +1381,11 @@ static int armada370_ecc_init(struct pxa
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ecc->strength = 16;
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return 1;
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- } else if (strength == 8 && page_size == 4096) {
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+ /*
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+ * Required ECC: 8-bit correction per 512 bytes
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+ * Select: 16-bit correction per 1024 bytes
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+ */
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+ } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
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info->ecc_bch = 1;
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info->chunk_size = 1024;
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info->spare_size = 0;
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@@ -1485,6 +1493,7 @@ KEEP_CONFIG:
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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ret = armada370_ecc_init(info, &chip->ecc,
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chip->ecc_strength_ds,
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+ chip->ecc_step_ds,
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mtd->writesize);
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else
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ret = pxa_ecc_init(info, &chip->ecc,
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