579 lines
14 KiB
C
579 lines
14 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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*/
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/*
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* Platform devices for Atheros SoCs
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*/
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#include <linux/autoconf.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include "ar531x.h"
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#define NO_PHY 0x1f
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static int is_5312 = 0;
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static struct platform_device *ar5312_devs[5];
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static struct resource ar5312_eth0_res[] = {
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{
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.name = "eth0_membase",
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.flags = IORESOURCE_MEM,
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.start = KSEG1ADDR(AR531X_ENET0),
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.end = KSEG1ADDR(AR531X_ENET0 + 0x2000),
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},
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{
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.name = "eth0_irq",
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.flags = IORESOURCE_IRQ,
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.start = AR5312_IRQ_ENET0_INTRS,
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.end = AR5312_IRQ_ENET0_INTRS,
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},
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};
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static struct ar531x_eth ar5312_eth0_data = {
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.phy = NO_PHY,
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.mac = 0,
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.reset_base = AR531X_RESET,
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.reset_mac = AR531X_RESET_ENET0,
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.reset_phy = AR531X_RESET_EPHY0,
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.phy_base = KSEG1ADDR(AR531X_ENET0),
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};
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static struct resource ar5312_eth1_res[] = {
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{
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.name = "eth1_membase",
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.flags = IORESOURCE_MEM,
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.start = KSEG1ADDR(AR531X_ENET1),
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.end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
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},
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{
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.name = "eth1_irq",
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.flags = IORESOURCE_IRQ,
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.start = AR5312_IRQ_ENET1_INTRS,
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.end = AR5312_IRQ_ENET1_INTRS,
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},
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};
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static struct ar531x_eth ar5312_eth1_data = {
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.phy = NO_PHY,
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.mac = 1,
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.reset_base = AR531X_RESET,
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.reset_mac = AR531X_RESET_ENET1,
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.reset_phy = AR531X_RESET_EPHY1,
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.phy_base = KSEG1ADDR(AR531X_ENET1),
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};
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static struct platform_device ar5312_eth[] = {
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{
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.id = 0,
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.name = "ar531x-eth",
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.dev.platform_data = &ar5312_eth0_data,
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.resource = ar5312_eth0_res,
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.num_resources = ARRAY_SIZE(ar5312_eth0_res)
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},
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{
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.id = 1,
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.name = "ar531x-eth",
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.dev.platform_data = &ar5312_eth1_data,
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.resource = ar5312_eth1_res,
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.num_resources = ARRAY_SIZE(ar5312_eth1_res)
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},
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};
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/*
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* AR2312/3 ethernet uses the PHY of ENET0, but the MAC
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* of ENET1. Atheros calls it 'twisted' for a reason :)
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*/
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static struct resource ar231x_eth0_res[] = {
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{
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.name = "eth0_membase",
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.flags = IORESOURCE_MEM,
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.start = KSEG1ADDR(AR531X_ENET1),
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.end = KSEG1ADDR(AR531X_ENET1 + 0x2000),
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},
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{
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.name = "eth0_irq",
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.flags = IORESOURCE_IRQ,
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.start = AR5312_IRQ_ENET1_INTRS,
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.end = AR5312_IRQ_ENET1_INTRS,
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},
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};
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static struct ar531x_eth ar231x_eth0_data = {
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.phy = 1,
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.mac = 1,
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.reset_base = AR531X_RESET,
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.reset_mac = AR531X_RESET_ENET1,
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.reset_phy = AR531X_RESET_EPHY1,
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.phy_base = KSEG1ADDR(AR531X_ENET0),
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};
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static struct platform_device ar231x_eth0 = {
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.id = 0,
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.name = "ar531x-eth",
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.dev.platform_data = &ar231x_eth0_data,
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.resource = ar231x_eth0_res,
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.num_resources = ARRAY_SIZE(ar231x_eth0_res)
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};
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static struct platform_device ar5312_wmac[] = {
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{
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.id = 0,
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.name = "ar531x-wmac",
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},
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{
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.id = 1,
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.name = "ar531x-wmac",
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},
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};
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static struct physmap_flash_data ar5312_flash_data = {
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.width = 2,
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};
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static struct resource ar5312_flash_resource = {
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.start = AR531X_FLASH,
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.end = AR531X_FLASH + 0x400000 - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ar5312_physmap_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &ar5312_flash_data,
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},
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.num_resources = 1,
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.resource = &ar5312_flash_resource,
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};
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/*
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* NB: This mapping size is larger than the actual flash size,
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* but this shouldn't be a problem here, because the flash
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* will simply be mapped multiple times.
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*/
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static char __init *ar5312_flash_limit(void)
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{
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u32 ctl;
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/*
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* Configure flash bank 0.
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* Assume 8M window size. Flash will be aliased if it's smaller
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*/
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ctl = FLASHCTL_E |
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FLASHCTL_AC_8M |
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FLASHCTL_RBLE |
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(0x01 << FLASHCTL_IDCY_S) |
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(0x07 << FLASHCTL_WST1_S) |
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(0x07 << FLASHCTL_WST2_S) |
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(sysRegRead(AR531X_FLASHCTL0) & FLASHCTL_MW);
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sysRegWrite(AR531X_FLASHCTL0, ctl);
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/* Disable other flash banks */
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sysRegWrite(AR531X_FLASHCTL1,
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sysRegRead(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
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sysRegWrite(AR531X_FLASHCTL2,
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sysRegRead(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
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return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
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}
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static struct ar531x_config __init *init_wmac(int unit)
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{
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struct ar531x_config *config;
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config = (struct ar531x_config *) kzalloc(sizeof(struct ar531x_config), GFP_KERNEL);
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config->board = board_config;
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config->radio = radio_config;
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config->unit = unit;
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config->tag = (u_int16_t) ((sysRegRead(AR531X_REV) >> AR531X_REV_WMAC_MIN_S) & AR531X_REV_CHIP);
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return config;
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}
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int __init ar5312_init_devices(void)
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{
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struct ar531x_boarddata *bcfg;
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char *radio, *c;
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int dev = 0;
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if (!is_5312)
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return 0;
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/* Locate board/radio config data */
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ar531x_find_config(ar5312_flash_limit());
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bcfg = (struct ar531x_boarddata *) board_config;
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/*
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* Chip IDs and hardware detection for some Atheros
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* models are really broken!
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*
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* Atheros uses a disabled WMAC0 and Silicon ID of AR5312
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* as indication for AR2312, which is otherwise
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* indistinguishable from the real AR5312.
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*/
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if (radio_config) {
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radio = radio_config + AR531X_RADIO_MASK_OFF;
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if ((*((u32 *) radio) & AR531X_RADIO0_MASK) == 0)
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bcfg->config |= BD_ISCASPER;
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} else
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radio = NULL;
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/* AR2313 has CPU minor rev. 10 */
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if ((current_cpu_data.processor_id & 0xff) == 0x0a)
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mips_machtype = MACH_ATHEROS_AR2313;
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/* AR2312 shares the same Silicon ID as AR5312 */
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else if (bcfg->config & BD_ISCASPER)
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mips_machtype = MACH_ATHEROS_AR2312;
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/* Everything else is probably AR5312 or compatible */
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else
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mips_machtype = MACH_ATHEROS_AR5312;
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ar5312_eth0_data.board_config = board_config;
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ar5312_eth1_data.board_config = board_config;
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ar5312_devs[dev++] = &ar5312_physmap_flash;
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if (!memcmp(bcfg->enet0Mac, "\xff\xff\xff\xff\xff\xff", 6))
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memcpy(bcfg->enet0Mac, bcfg->enet1Mac, 6);
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if (memcmp(bcfg->enet0Mac, bcfg->enet1Mac, 6) == 0) {
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/* ENET0 and ENET1 have the same mac.
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* Increment the one from ENET1 */
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c = bcfg->enet1Mac + 5;
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while ((c >= (char *) bcfg->enet1Mac) && !(++(*c)))
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c--;
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}
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switch(mips_machtype) {
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case MACH_ATHEROS_AR5312:
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ar5312_eth0_data.macaddr = bcfg->enet0Mac;
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ar5312_eth1_data.macaddr = bcfg->enet1Mac;
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ar5312_devs[dev++] = &ar5312_eth[0];
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ar5312_devs[dev++] = &ar5312_eth[1];
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break;
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case MACH_ATHEROS_AR2312:
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case MACH_ATHEROS_AR2313:
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ar231x_eth0_data.macaddr = bcfg->enet0Mac;
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ar5312_devs[dev++] = &ar231x_eth0;
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ar5312_flash_data.width = 1;
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break;
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}
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if (radio) {
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if (*((u32 *) radio) & AR531X_RADIO0_MASK) {
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ar5312_wmac[0].dev.platform_data = init_wmac(0);
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ar5312_devs[dev++] = &ar5312_wmac[0];
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}
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if (*((u32 *) radio) & AR531X_RADIO1_MASK) {
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ar5312_wmac[1].dev.platform_data = init_wmac(1);
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ar5312_devs[dev++] = &ar5312_wmac[1];
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}
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}
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return platform_add_devices(ar5312_devs, dev);
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}
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/*
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* Called when an interrupt is received, this function
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* determines exactly which interrupt it was, and it
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* invokes the appropriate handler.
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*
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* Implicitly, we also define interrupt priority by
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* choosing which to dispatch first.
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*/
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asmlinkage void ar5312_irq_dispatch(void)
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{
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int pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP2)
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do_IRQ(AR5312_IRQ_WLAN0_INTRS);
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else if (pending & CAUSEF_IP3)
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do_IRQ(AR5312_IRQ_ENET0_INTRS);
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else if (pending & CAUSEF_IP4)
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do_IRQ(AR5312_IRQ_ENET1_INTRS);
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else if (pending & CAUSEF_IP5)
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do_IRQ(AR5312_IRQ_WLAN1_INTRS);
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else if (pending & CAUSEF_IP6) {
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unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
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if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
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do_IRQ(AR531X_MISC_IRQ_TIMER);
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(void)sysRegRead(AR531X_TIMER);
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} else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
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do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
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else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
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do_IRQ(AR531X_MISC_IRQ_UART0);
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else if (ar531x_misc_intrs & AR531X_ISR_WD)
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do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
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else
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do_IRQ(AR531X_MISC_IRQ_NONE);
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} else if (pending & CAUSEF_IP7) {
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do_IRQ(AR531X_IRQ_CPU_CLOCK);
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}
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else
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do_IRQ(AR531X_IRQ_NONE);
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}
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static void ar5312_halt(void)
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{
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while (1);
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}
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static void ar5312_power_off(void)
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{
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ar5312_halt();
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}
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static void ar5312_restart(char *command)
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{
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/* reset the system */
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for(;;) sysRegWrite(AR531X_RESET, AR531X_RESET_SYSTEM);
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}
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/*
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* This table is indexed by bits 5..4 of the CLOCKCTL1 register
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* to determine the predevisor value.
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*/
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static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
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1,
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2,
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4,
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5
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};
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static unsigned int __init ar5312_cpu_frequency(void)
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{
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unsigned int result;
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unsigned int predivide_mask, predivide_shift;
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unsigned int multiplier_mask, multiplier_shift;
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unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
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unsigned int doubler_mask;
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unsigned int wisoc_revision;
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/* Trust the bootrom's idea of cpu frequency. */
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if ((result = sysRegRead(AR5312_SCRATCH)))
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return result;
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wisoc_revision = (sysRegRead(AR531X_REV) & AR531X_REV_MAJ) >> AR531X_REV_MAJ_S;
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if (wisoc_revision == AR531X_REV_MAJ_AR2313) {
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predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
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predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
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multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
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multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
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doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
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} else { /* AR5312 and AR2312 */
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predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
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predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
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multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
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multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
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doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
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}
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/*
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* Clocking is derived from a fixed 40MHz input clock.
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*
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* cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
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* sysFreq = cpuFreq / 4 (used for APB clock, serial,
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* flash, Timer, Watchdog Timer)
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*
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* cntFreq = cpuFreq / 2 (use for CPU count/compare)
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*
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* So, for example, with a PLL multiplier of 5, we have
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*
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* cpuFreq = 200MHz
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* sysFreq = 50MHz
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* cntFreq = 100MHz
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*
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* We compute the CPU frequency, based on PLL settings.
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*/
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clockCtl1 = sysRegRead(AR5312_CLOCKCTL1);
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preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
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preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
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multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
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if (clockCtl1 & doubler_mask) {
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multiplier = multiplier << 1;
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}
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return (40000000 / preDivisor) * multiplier;
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}
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static inline int ar5312_sys_frequency(void)
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{
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return ar5312_cpu_frequency() / 4;
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}
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static void __init ar5312_time_init(void)
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{
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mips_hpt_frequency = ar5312_cpu_frequency() / 2;
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}
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/* Enable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5312_misc_intr_enable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR531X_IMR);
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imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
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sysRegWrite(AR531X_IMR, imr);
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sysRegRead(AR531X_IMR); /* flush write buffer */
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}
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/* Disable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5312_misc_intr_disable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR531X_IMR);
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imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
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sysRegWrite(AR531X_IMR, imr);
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sysRegRead(AR531X_IMR); /* flush write buffer */
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}
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/* Turn on the specified AR531X_MISC_IRQ interrupt */
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static unsigned int
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ar5312_misc_intr_startup(unsigned int irq)
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{
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ar5312_misc_intr_enable(irq);
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return 0;
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}
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|
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/* Turn off the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5312_misc_intr_shutdown(unsigned int irq)
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{
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ar5312_misc_intr_disable(irq);
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}
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static void
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ar5312_misc_intr_ack(unsigned int irq)
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{
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ar5312_misc_intr_disable(irq);
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}
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static void
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ar5312_misc_intr_end(unsigned int irq)
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|
{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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ar5312_misc_intr_enable(irq);
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}
|
|
|
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static struct irq_chip ar5312_misc_intr_controller = {
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.typename = "AR5312 misc",
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.startup = ar5312_misc_intr_startup,
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.shutdown = ar5312_misc_intr_shutdown,
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.enable = ar5312_misc_intr_enable,
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.disable = ar5312_misc_intr_disable,
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.ack = ar5312_misc_intr_ack,
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.end = ar5312_misc_intr_end,
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|
};
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|
|
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static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
|
|
{
|
|
u32 proc1 = sysRegRead(AR531X_PROC1);
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|
u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
|
|
u32 dma1 = sysRegRead(AR531X_DMA1);
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u32 dmaAddr = sysRegRead(AR531X_DMAADDR); /* clears error state */
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|
|
|
printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
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procAddr, proc1, dmaAddr, dma1);
|
|
|
|
machine_restart("AHB error"); /* Catastrophic failure */
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
|
|
static struct irqaction ar5312_ahb_proc_interrupt = {
|
|
.handler = ar5312_ahb_proc_handler,
|
|
.flags = SA_INTERRUPT,
|
|
.name = "ar5312_ahb_proc_interrupt",
|
|
};
|
|
|
|
|
|
static struct irqaction cascade = {
|
|
.handler = no_action,
|
|
.flags = SA_INTERRUPT,
|
|
.name = "cascade",
|
|
};
|
|
|
|
void __init ar5312_misc_intr_init(int irq_base)
|
|
{
|
|
int i;
|
|
|
|
for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
|
|
irq_desc[i].status = IRQ_DISABLED;
|
|
irq_desc[i].action = NULL;
|
|
irq_desc[i].depth = 1;
|
|
irq_desc[i].chip = &ar5312_misc_intr_controller;
|
|
}
|
|
setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
|
|
setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
|
|
}
|
|
|
|
void __init ar5312_prom_init(void)
|
|
{
|
|
u32 memsize, memcfg, bank0AC, bank1AC;
|
|
|
|
is_5312 = 1;
|
|
|
|
/* Detect memory size */
|
|
memcfg = sysRegRead(AR531X_MEM_CFG1);
|
|
bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
|
|
bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
|
|
memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
|
|
+ (bank1AC ? (1 << (bank1AC+1)) : 0);
|
|
memsize <<= 20;
|
|
add_memory_region(0, memsize, BOOT_MEM_RAM);
|
|
|
|
/* Initialize it to AR5312 for now. Real detection will be done
|
|
* in ar5312_init_devices() */
|
|
mips_machtype = MACH_ATHEROS_AR5312;
|
|
}
|
|
|
|
void __init ar5312_plat_setup(void)
|
|
{
|
|
/* Clear any lingering AHB errors */
|
|
sysRegRead(AR531X_PROCADDR);
|
|
sysRegRead(AR531X_DMAADDR);
|
|
sysRegWrite(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
|
|
|
|
board_time_init = ar5312_time_init;
|
|
|
|
_machine_restart = ar5312_restart;
|
|
_machine_halt = ar5312_halt;
|
|
pm_power_off = ar5312_power_off;
|
|
|
|
serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
|
|
}
|
|
|
|
arch_initcall(ar5312_init_devices);
|