02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
74 lines
2.0 KiB
Diff
74 lines
2.0 KiB
Diff
From c9bfaadf8973cb4d9074e80c4bf8708deca62712 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Sat, 22 Feb 2014 22:35:54 +0100
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Subject: [PATCH] ARM: dt: sun7i: Add A20 SPI controller nodes
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The A20 has 4 SPI controllers compatible with the one found in the A10. Add
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them in the DT.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun7i-a20.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++
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1 file changed, 44 insertions(+)
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -401,6 +401,28 @@
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#size-cells = <1>;
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ranges;
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+ spi0: spi@01c05000 {
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+ compatible = "allwinner,sun4i-a10-spi";
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+ reg = <0x01c05000 0x1000>;
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+ interrupts = <0 10 4>;
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+ clocks = <&ahb_gates 20>, <&spi0_clk>;
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+ clock-names = "ahb", "mod";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi1: spi@01c06000 {
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+ compatible = "allwinner,sun4i-a10-spi";
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+ reg = <0x01c06000 0x1000>;
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+ interrupts = <0 11 4>;
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+ clocks = <&ahb_gates 21>, <&spi1_clk>;
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+ clock-names = "ahb", "mod";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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emac: ethernet@01c0b000 {
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compatible = "allwinner,sun4i-a10-emac";
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reg = <0x01c0b000 0x1000>;
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@@ -415,6 +437,28 @@
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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+ };
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+
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+ spi2: spi@01c17000 {
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+ compatible = "allwinner,sun4i-a10-spi";
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+ reg = <0x01c17000 0x1000>;
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+ interrupts = <0 12 4>;
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+ clocks = <&ahb_gates 22>, <&spi2_clk>;
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+ clock-names = "ahb", "mod";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ spi3: spi@01c1f000 {
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+ compatible = "allwinner,sun4i-a10-spi";
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+ reg = <0x01c1f000 0x1000>;
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+ interrupts = <0 50 4>;
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+ clocks = <&ahb_gates 23>, <&spi3_clk>;
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+ clock-names = "ahb", "mod";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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};
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pio: pinctrl@01c20800 {
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