02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
129 lines
3.4 KiB
Diff
129 lines
3.4 KiB
Diff
From 0643a93746775da2189ab0afd8f748afcaa791c5 Mon Sep 17 00:00:00 2001
|
|
From: Hans de Goede <hdegoede@redhat.com>
|
|
Date: Fri, 7 Feb 2014 16:21:49 +0100
|
|
Subject: [PATCH] clk: sunxi: Add support for USB clock-register reset bits
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
The usb-clk register is special in that it not only contains clk gate bits,
|
|
but also has a few reset bits. This commit adds support for this by allowing
|
|
gates type sunxi clks to also register a reset controller.
|
|
|
|
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
|
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Signed-off-by: Emilio López <emilio@elopez.com.ar>
|
|
---
|
|
drivers/clk/sunxi/clk-sunxi.c | 71 +++++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 71 insertions(+)
|
|
|
|
--- a/drivers/clk/sunxi/clk-sunxi.c
|
|
+++ b/drivers/clk/sunxi/clk-sunxi.c
|
|
@@ -18,6 +18,7 @@
|
|
#include <linux/clkdev.h>
|
|
#include <linux/of.h>
|
|
#include <linux/of_address.h>
|
|
+#include <linux/reset-controller.h>
|
|
|
|
#include "clk-factors.h"
|
|
|
|
@@ -688,6 +689,59 @@ static void __init sunxi_divider_clk_set
|
|
|
|
|
|
/**
|
|
+ * sunxi_gates_reset... - reset bits in leaf gate clk registers handling
|
|
+ */
|
|
+
|
|
+struct gates_reset_data {
|
|
+ void __iomem *reg;
|
|
+ spinlock_t *lock;
|
|
+ struct reset_controller_dev rcdev;
|
|
+};
|
|
+
|
|
+static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev,
|
|
+ unsigned long id)
|
|
+{
|
|
+ struct gates_reset_data *data = container_of(rcdev,
|
|
+ struct gates_reset_data,
|
|
+ rcdev);
|
|
+ unsigned long flags;
|
|
+ u32 reg;
|
|
+
|
|
+ spin_lock_irqsave(data->lock, flags);
|
|
+
|
|
+ reg = readl(data->reg);
|
|
+ writel(reg & ~BIT(id), data->reg);
|
|
+
|
|
+ spin_unlock_irqrestore(data->lock, flags);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev,
|
|
+ unsigned long id)
|
|
+{
|
|
+ struct gates_reset_data *data = container_of(rcdev,
|
|
+ struct gates_reset_data,
|
|
+ rcdev);
|
|
+ unsigned long flags;
|
|
+ u32 reg;
|
|
+
|
|
+ spin_lock_irqsave(data->lock, flags);
|
|
+
|
|
+ reg = readl(data->reg);
|
|
+ writel(reg | BIT(id), data->reg);
|
|
+
|
|
+ spin_unlock_irqrestore(data->lock, flags);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct reset_control_ops sunxi_gates_reset_ops = {
|
|
+ .assert = sunxi_gates_reset_assert,
|
|
+ .deassert = sunxi_gates_reset_deassert,
|
|
+};
|
|
+
|
|
+/**
|
|
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
|
|
*/
|
|
|
|
@@ -695,6 +749,7 @@ static void __init sunxi_divider_clk_set
|
|
|
|
struct gates_data {
|
|
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
|
|
+ u32 reset_mask;
|
|
};
|
|
|
|
static const struct gates_data sun4i_axi_gates_data __initconst = {
|
|
@@ -765,6 +820,7 @@ static void __init sunxi_gates_clk_setup
|
|
struct gates_data *data)
|
|
{
|
|
struct clk_onecell_data *clk_data;
|
|
+ struct gates_reset_data *reset_data;
|
|
const char *clk_parent;
|
|
const char *clk_name;
|
|
void *reg;
|
|
@@ -808,6 +864,21 @@ static void __init sunxi_gates_clk_setup
|
|
clk_data->clk_num = i;
|
|
|
|
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
+
|
|
+ /* Register a reset controler for gates with reset bits */
|
|
+ if (data->reset_mask == 0)
|
|
+ return;
|
|
+
|
|
+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
|
|
+ if (!reset_data)
|
|
+ return;
|
|
+
|
|
+ reset_data->reg = reg;
|
|
+ reset_data->lock = &clk_lock;
|
|
+ reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1;
|
|
+ reset_data->rcdev.ops = &sunxi_gates_reset_ops;
|
|
+ reset_data->rcdev.of_node = node;
|
|
+ reset_controller_register(&reset_data->rcdev);
|
|
}
|
|
|
|
|