43cc8c3ebe
Use the CFE_EPTSEAL to tell them apart at runtime. Added for now only for the 3.14 until properly tested. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 41296
125 lines
4.7 KiB
Diff
125 lines
4.7 KiB
Diff
--- a/arch/mips/bcm63xx/usb-common.c
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+++ b/arch/mips/bcm63xx/usb-common.c
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@@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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reg |= USBH_PRIV_SETUP_IOC_MASK;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+ } else if (BCMCPU_IS_6318()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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+ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
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+ reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
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+ reg |= USBH_PRIV_SETUP_IOC_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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+ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
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+ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
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}
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spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
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@@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
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reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
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reg |= USBH_PRIV_SETUP_IOC_MASK;
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bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
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+ } else if (BCMCPU_IS_6318()) {
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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+ reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
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+ reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
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+ reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
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+ reg |= USBH_PRIV_SETUP_IOC_MASK;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
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+ reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
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+
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+ reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
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+ reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
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+ bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
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}
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spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -680,6 +680,12 @@
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#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
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#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
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+#define GPIO_PINMUX_SEL0_6318 0x1c
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+#define GPIO_PINMUX_SEL0_GPIO13_SHIFT 26
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+#define GPIO_PINMUX_SEL0_GPIO13_MASK (0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
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+#define GPIO_PINMUX_SEL0_GPIO13_PWRON (1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
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+#define GPIO_PINMUX_SEL0_GPIO13_LED (2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
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+#define GPIO_PINMUX_SEL0_GPIO13_GPIO (3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
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#define GPIO_PINMUX_OTHR_REG 0x24
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#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
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@@ -998,6 +1004,7 @@
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#define USBH_PRIV_SWAP_6358_REG 0x0
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#define USBH_PRIV_SWAP_6368_REG 0x1c
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+#define USBH_PRIV_SWAP_6318_REG 0x0c
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#define USBH_PRIV_SWAP_USBD_SHIFT 6
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#define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
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@@ -1023,6 +1030,13 @@
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#define USBH_PRIV_SETUP_IOC_SHIFT 4
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#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
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+#define USBH_PRIV_SETUP_6318_REG 0x00
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+#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04
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+#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27)
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+#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31)
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+#define USBH_PRIV_SIM_CTRL_6318_REG 0x20
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+#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5)
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+
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/*************************************************************************
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* _REG relative to RSET_USBD
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--- a/arch/mips/bcm63xx/boards/board_common.c
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+++ b/arch/mips/bcm63xx/boards/board_common.c
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@@ -129,6 +129,15 @@ void __init board_early_setup(const stru
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}
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bcm_gpio_writel(val, GPIO_MODE_REG);
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+
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+#if IS_ENABLED(CONFIG_USB)
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+ if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) {
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+ val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318);
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+ val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK;
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+ val |= GPIO_PINMUX_SEL0_GPIO13_PWRON;
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+ bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318);
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+ }
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+#endif
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}
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--- a/arch/mips/bcm63xx/Kconfig
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+++ b/arch/mips/bcm63xx/Kconfig
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@@ -22,6 +22,8 @@ config BCM63XX_CPU_6318
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bool "support 6318 CPU"
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select SYS_HAS_CPU_BMIPS32_3300
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select HW_HAS_PCI
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+ select BCM63XX_OHCI
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+ select BCM63XX_EHCI
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config BCM63XX_CPU_6328
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bool "support 6328 CPU"
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