120 lines
3.1 KiB
Diff
120 lines
3.1 KiB
Diff
From 2fdf8dcff3ffaa806e9f9d7f1c1bd876222cff4d Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 11 Jun 2012 13:39:32 +0200
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Subject: [PATCH 07/34] MIPS: ath79: register platform devices for the PCI controllers
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/pci.c | 87 +++++++++++++++++++++++++++++++++++++++++++-----
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1 files changed, 78 insertions(+), 9 deletions(-)
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--- a/arch/mips/ath79/pci.c
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+++ b/arch/mips/ath79/pci.c
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@@ -14,6 +14,8 @@
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#include <linux/init.h>
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#include <linux/pci.h>
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+#include <linux/resource.h>
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+#include <linux/platform_device.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/irq.h>
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@@ -110,21 +112,88 @@ void __init ath79_pci_set_plat_dev_init(
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ath79_pci_plat_dev_init = func;
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}
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-int __init ath79_register_pci(void)
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+static struct platform_device *
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+ath79_register_pci_ar71xx(void)
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{
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- if (soc_is_ar71xx())
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- return ar71xx_pcibios_init();
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+ struct platform_device *pdev;
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+ struct resource res[2];
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+
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+ memset(res, 0, sizeof(res));
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- if (soc_is_ar724x())
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- return ar724x_pcibios_init(ATH79_CPU_IRQ_IP2);
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+ res[0].name = "cfg_base";
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+ res[0].flags = IORESOURCE_MEM;
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+ res[0].start = AR71XX_PCI_CFG_BASE;
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+ res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
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+
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+ res[1].flags = IORESOURCE_IRQ;
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+ res[1].start = ATH79_CPU_IRQ_IP2;
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+ res[1].end = ATH79_CPU_IRQ_IP2;
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+
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+ pdev = platform_device_register_simple("ar71xx-pci", -1,
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+ res, ARRAY_SIZE(res));
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+ return pdev;
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+}
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- if (soc_is_ar9342() || soc_is_ar9344()) {
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+static struct platform_device *
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+ath79_register_pci_ar724x(int id,
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+ unsigned long cfg_base,
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+ unsigned long ctrl_base,
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+ int irq)
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+{
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+ struct platform_device *pdev;
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+ struct resource res[3];
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+
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+ memset(res, 0, sizeof(res));
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+
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+ res[0].name = "cfg_base";
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+ res[0].flags = IORESOURCE_MEM;
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+ res[0].start = cfg_base;
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+ res[0].end = cfg_base + AR724X_PCI_CFG_SIZE - 1;
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+
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+ res[1].name = "ctrl_base";
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+ res[1].flags = IORESOURCE_MEM;
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+ res[1].start = ctrl_base;
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+ res[1].end = ctrl_base + AR724X_PCI_CTRL_SIZE - 1;
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+
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+ res[2].flags = IORESOURCE_IRQ;
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+ res[2].start = irq;
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+ res[2].end = irq;
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+
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+ pdev = platform_device_register_simple("ar724x-pci", id,
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+ res, ARRAY_SIZE(res));
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+ return pdev;
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+}
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+
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+int __init ath79_register_pci(void)
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+{
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+ struct platform_device *pdev = NULL;
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+
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+ if (soc_is_ar71xx()) {
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+ pdev = ath79_register_pci_ar71xx();
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+ } else if (soc_is_ar724x()) {
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+ pdev = ath79_register_pci_ar724x(-1,
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+ AR724X_PCI_CFG_BASE,
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+ AR724X_PCI_CTRL_BASE,
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+ ATH79_CPU_IRQ_IP2);
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+ } else if (soc_is_ar9342() ||
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+ soc_is_ar9344()) {
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u32 bootstrap;
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bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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- if (bootstrap & AR934X_BOOTSTRAP_PCIE_RC)
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- return ar724x_pcibios_init(ATH79_IP2_IRQ(0));
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+ if ((bootstrap & AR934X_BOOTSTRAP_PCIE_RC) == 0)
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+ return -ENODEV;
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+
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+ pdev = ath79_register_pci_ar724x(-1,
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+ AR724X_PCI_CFG_BASE,
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+ AR724X_PCI_CTRL_BASE,
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+ ATH79_IP2_IRQ(0));
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+ } else {
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+ /* No PCI support */
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+ return -ENODEV;
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}
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- return -ENODEV;
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+ if (!pdev)
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+ pr_err("unable to register PCI controller device\n");
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+
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+ return pdev ? 0 : -ENODEV;
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}
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