490 lines
14 KiB
Diff
490 lines
14 KiB
Diff
From 02d9df56be1ba23c7bec51c94e5d2ac0d13d2d78 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 11 Aug 2011 14:35:02 +0200
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Subject: [PATCH 07/24] MIPS: lantiq: add support for FALC-ON GPIOs
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FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds
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the new driver.
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: linux-mips@linux-mips.org
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---
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arch/mips/lantiq/falcon/Makefile | 2 +-
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arch/mips/lantiq/falcon/devices.c | 41 ++++
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arch/mips/lantiq/falcon/devices.h | 2 +
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arch/mips/lantiq/falcon/gpio.c | 398 +++++++++++++++++++++++++++++++++++++
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4 files changed, 442 insertions(+), 1 deletions(-)
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create mode 100644 arch/mips/lantiq/falcon/gpio.c
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--- a/arch/mips/lantiq/falcon/Makefile
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+++ b/arch/mips/lantiq/falcon/Makefile
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@@ -1 +1 @@
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-obj-y := clk.o prom.o reset.o sysctrl.o devices.o
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+obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
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--- a/arch/mips/lantiq/falcon/devices.c
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+++ b/arch/mips/lantiq/falcon/devices.c
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@@ -9,6 +9,7 @@
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#include <linux/platform_device.h>
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#include <linux/mtd/nand.h>
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+#include <linux/gpio.h>
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#include <lantiq_soc.h>
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@@ -85,3 +86,43 @@ falcon_register_nand(void)
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{
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platform_device_register(<q_flash_nand);
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}
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+
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+/* gpio */
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+#define DECLARE_GPIO_RES(port) \
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+static struct resource falcon_gpio ## port ## _res[] = { \
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+ MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \
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+ LTQ_GPIO ## port ## _SIZE), \
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+ MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \
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+ LTQ_PADCTRL ## port ## _SIZE), \
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+ IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \
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+}
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+DECLARE_GPIO_RES(0);
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+DECLARE_GPIO_RES(1);
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+DECLARE_GPIO_RES(2);
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+DECLARE_GPIO_RES(3);
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+DECLARE_GPIO_RES(4);
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+
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+void __init
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+falcon_register_gpio(void)
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+{
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+ platform_device_register_simple("falcon_gpio", 0,
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+ falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res));
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+ platform_device_register_simple("falcon_gpio", 1,
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+ falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
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+ platform_device_register_simple("falcon_gpio", 2,
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+ falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
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+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
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+ ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 |
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+ ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2);
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+}
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+
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+void __init
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+falcon_register_gpio_extra(void)
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+{
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+ platform_device_register_simple("falcon_gpio", 3,
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+ falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
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+ platform_device_register_simple("falcon_gpio", 4,
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+ falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
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+ ltq_sysctl_activate(SYSCTL_SYS1,
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+ ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
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+}
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--- a/arch/mips/lantiq/falcon/devices.h
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+++ b/arch/mips/lantiq/falcon/devices.h
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@@ -14,5 +14,7 @@
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#include "../devices.h"
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extern void falcon_register_nand(void);
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+extern void falcon_register_gpio(void);
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+extern void falcon_register_gpio_extra(void);
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#endif
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--- /dev/null
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+++ b/arch/mips/lantiq/falcon/gpio.c
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@@ -0,0 +1,398 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
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+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/gpio.h>
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+#include <linux/interrupt.h>
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+#include <linux/slab.h>
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+#include <linux/platform_device.h>
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+
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+#include <lantiq_soc.h>
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+
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+/* Multiplexer Control Register */
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+#define LTQ_PADC_MUX(x) (x * 0x4)
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+/* Pad Control Availability Register */
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+#define LTQ_PADC_AVAIL 0x000000F0
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+
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+/* Data Output Register */
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+#define LTQ_GPIO_OUT 0x00000000
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+/* Data Input Register */
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+#define LTQ_GPIO_IN 0x00000004
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+/* Direction Register */
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+#define LTQ_GPIO_DIR 0x00000008
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+/* External Interrupt Control Register 0 */
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+#define LTQ_GPIO_EXINTCR0 0x00000018
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+/* External Interrupt Control Register 1 */
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+#define LTQ_GPIO_EXINTCR1 0x0000001C
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+/* IRN Capture Register */
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+#define LTQ_GPIO_IRNCR 0x00000020
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+/* IRN Interrupt Configuration Register */
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+#define LTQ_GPIO_IRNCFG 0x0000002C
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+/* IRN Interrupt Enable Set Register */
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+#define LTQ_GPIO_IRNRNSET 0x00000030
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+/* IRN Interrupt Enable Clear Register */
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+#define LTQ_GPIO_IRNENCLR 0x00000034
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+/* Output Set Register */
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+#define LTQ_GPIO_OUTSET 0x00000040
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+/* Output Cler Register */
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+#define LTQ_GPIO_OUTCLR 0x00000044
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+/* Direction Clear Register */
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+#define LTQ_GPIO_DIRSET 0x00000048
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+/* Direction Set Register */
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+#define LTQ_GPIO_DIRCLR 0x0000004C
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+
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+/* turn a gpio_chip into a falcon_gpio_port */
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+#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
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+/* turn a irq_data into a falcon_gpio_port */
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+#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
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+
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+#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg)
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+#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg)
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+#define ltq_pad_w32_mask(c, clear, set, reg) \
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+ ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg)
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+
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+#define ltq_port_r32(p, reg) ltq_r32(p->port + reg)
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+#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg)
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+#define ltq_port_w32_mask(p, clear, set, reg) \
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+ ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg)
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+
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+#define MAX_PORTS 5
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+#define PINS_PER_PORT 32
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+
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+struct falcon_gpio_port {
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+ struct gpio_chip gpio_chip;
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+ void __iomem *pad;
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+ void __iomem *port;
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+ unsigned int irq_base;
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+ unsigned int chained_irq;
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+};
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+
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+static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
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+
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+int gpio_to_irq(unsigned int gpio)
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+{
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+ return __gpio_to_irq(gpio);
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+}
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+EXPORT_SYMBOL(gpio_to_irq);
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+
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+int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
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+{
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+ int port = pin / 100;
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+ int offset = pin % 100;
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+ struct falcon_gpio_port *gpio_port;
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+
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+ if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS))
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+ return -EINVAL;
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+
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+ gpio_port = <q_gpio_port[port];
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+ ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset));
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL(ltq_gpio_mux_set);
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+
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+int ltq_gpio_request(unsigned int pin, unsigned int val,
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+ unsigned int dir, const char *name)
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+{
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+ int port = pin / 100;
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+ int offset = pin % 100;
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+
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+ if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
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+ return -EINVAL;
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+
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+ if (gpio_request(pin, name)) {
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+ pr_err("failed to setup lantiq gpio: %s\n", name);
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+ return -EBUSY;
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+ }
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+
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+ if (dir)
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+ gpio_direction_output(pin, 1);
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+ else
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+ gpio_direction_input(pin);
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+
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+ return ltq_gpio_mux_set(pin, val);
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+}
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+EXPORT_SYMBOL(ltq_gpio_request);
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+
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+static int
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+falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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+{
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+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR);
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+
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+ return 0;
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+}
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+
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+static void
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+falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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+{
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+ if (value)
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+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET);
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+ else
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+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR);
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+}
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+
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+static int
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+falcon_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned int offset, int value)
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+{
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+ falcon_gpio_set(chip, offset, value);
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+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET);
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+
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+ return 0;
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+}
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+
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+static int
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+falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
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+{
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+ if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1)
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+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1;
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+ else
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+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1;
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+}
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+
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+static int
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+falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
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+{
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+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
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+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
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+ return -EBUSY;
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+ /* switch on gpio function */
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+ ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset));
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+ return 0;
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+ }
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+
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+ return -ENODEV;
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+}
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+
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+static void
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+falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
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+{
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+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
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+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
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+ return;
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+ /* switch off gpio function */
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+ ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset));
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+ }
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+}
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+
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+static int
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+falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
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+{
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+ return ctop(chip)->irq_base + offset;
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+}
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+
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+static void
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+falcon_gpio_disable_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
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+}
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+
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+static void
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+falcon_gpio_enable_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1)
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+ /* switch on gpio function */
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+ ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset));
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+
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+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET);
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+}
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+
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+static void
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+falcon_gpio_ack_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
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+}
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+
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+static void
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+falcon_gpio_mask_and_ack_irq(struct irq_data *d)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+
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+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
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+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
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+}
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+
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+static struct irq_chip falcon_gpio_irq_chip;
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+static int
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+falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
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+{
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+ unsigned int offset = d->irq - itop(d)->irq_base;
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+ unsigned int mask = 1 << offset;
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+
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+ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
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+ return 0;
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+
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+ if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
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+ /* level triggered */
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+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG);
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+ irq_set_chip_and_handler_name(d->irq,
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+ &falcon_gpio_irq_chip, handle_level_irq, "mux");
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+ } else {
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+ /* edge triggered */
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+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG);
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+ irq_set_chip_and_handler_name(d->irq,
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+ &falcon_gpio_irq_chip, handle_simple_irq, "mux");
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+ }
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+
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+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
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+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1);
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+ } else {
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+ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
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+ /* positive logic: rising edge, high level */
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+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
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+ else
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+ /* negative logic: falling edge, low level */
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+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0);
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+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1);
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+ }
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+
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+ return gpio_direction_input(itop(d)->gpio_chip.base + offset);
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+}
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+
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+static void
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+falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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+{
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+ struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
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+ unsigned long irncr;
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+ int offset;
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+
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+ /* acknowledge interrupt */
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+ irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR);
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+ ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR);
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+
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+ desc->irq_data.chip->irq_ack(&desc->irq_data);
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+
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+ for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
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+ generic_handle_irq(gpio_port->irq_base + offset);
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+}
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+
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+static struct irq_chip falcon_gpio_irq_chip = {
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+ .name = "gpio_irq_mux",
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+ .irq_mask = falcon_gpio_disable_irq,
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+ .irq_unmask = falcon_gpio_enable_irq,
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+ .irq_ack = falcon_gpio_ack_irq,
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+ .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
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+ .irq_set_type = falcon_gpio_irq_type,
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+};
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+
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+static struct irqaction gpio_cascade = {
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+ .handler = no_action,
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+ .flags = IRQF_DISABLED,
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+ .name = "gpio_cascade",
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+};
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+
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+static int
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+falcon_gpio_probe(struct platform_device *pdev)
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+{
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+ struct falcon_gpio_port *gpio_port;
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+ int ret, i;
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+ struct resource *gpiores, *padres;
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+ int irq;
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+
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+ if (pdev->id >= MAX_PORTS)
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+ return -ENODEV;
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+
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+ gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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+ irq = platform_get_irq(pdev, 0);
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+ if (!gpiores || !padres)
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+ return -ENODEV;
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+
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+ gpio_port = <q_gpio_port[pdev->id];
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+ gpio_port->gpio_chip.label = "falcon-gpio";
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+ gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
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+ gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
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+ gpio_port->gpio_chip.get = falcon_gpio_get;
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+ gpio_port->gpio_chip.set = falcon_gpio_set;
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+ gpio_port->gpio_chip.request = falcon_gpio_request;
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+ gpio_port->gpio_chip.free = falcon_gpio_free;
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+ gpio_port->gpio_chip.base = 100 * pdev->id;
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+ gpio_port->gpio_chip.ngpio = 32;
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+ gpio_port->gpio_chip.dev = &pdev->dev;
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+
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+ gpio_port->port = ltq_remap_resource(gpiores);
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+ gpio_port->pad = ltq_remap_resource(padres);
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+
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+ if (!gpio_port->port || !gpio_port->pad) {
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+ dev_err(&pdev->dev, "Could not map io ranges\n");
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+ ret = -ENOMEM;
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+ goto err;
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+ }
|
|
+
|
|
+ if (irq > 0) {
|
|
+ /* irq_chip support */
|
|
+ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
|
|
+ gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id);
|
|
+
|
|
+ for (i = 0; i < 32; i++) {
|
|
+ irq_set_chip_and_handler_name(gpio_port->irq_base + i,
|
|
+ &falcon_gpio_irq_chip, handle_simple_irq,
|
|
+ "mux");
|
|
+ irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
|
|
+ /* set to negative logic (falling edge, low level) */
|
|
+ ltq_port_w32_mask(gpio_port, 0, 1 << i,
|
|
+ LTQ_GPIO_EXINTCR0);
|
|
+ }
|
|
+
|
|
+ gpio_port->chained_irq = irq;
|
|
+ setup_irq(irq, &gpio_cascade);
|
|
+ irq_set_handler_data(irq, gpio_port);
|
|
+ irq_set_chained_handler(irq, falcon_gpio_irq_handler);
|
|
+ }
|
|
+
|
|
+ ret = gpiochip_add(&gpio_port->gpio_chip);
|
|
+ if (ret < 0) {
|
|
+ dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
|
|
+ pdev->id, ret);
|
|
+ goto err;
|
|
+ }
|
|
+ platform_set_drvdata(pdev, gpio_port);
|
|
+ return ret;
|
|
+
|
|
+err:
|
|
+ dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
|
|
+ if (gpiores)
|
|
+ release_resource(gpiores);
|
|
+ if (padres)
|
|
+ release_resource(padres);
|
|
+
|
|
+ if (gpio_port->port)
|
|
+ iounmap(gpio_port->port);
|
|
+ if (gpio_port->pad)
|
|
+ iounmap(gpio_port->pad);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static struct platform_driver falcon_gpio_driver = {
|
|
+ .probe = falcon_gpio_probe,
|
|
+ .driver = {
|
|
+ .name = "falcon_gpio",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+int __init
|
|
+falcon_gpio_init(void)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
|
|
+ ret = platform_driver_register(&falcon_gpio_driver);
|
|
+ if (ret)
|
|
+ pr_err("falcon_gpio: Error registering platform driver!");
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+postcore_initcall(falcon_gpio_init);
|