db36359f48
Remove the non runtime detect code since its effectiveness is dubious and almost never used. Also update affinity patches to work on top of it. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 39268
184 lines
6.5 KiB
Diff
184 lines
6.5 KiB
Diff
From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 25 Apr 2013 00:24:06 +0200
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Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to
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irq_{stat,mask}*
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The SMP capable irq controllers have two interupt output pins which are
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controlled through separate registers, so make the variables arrays.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 51 ++++++++++++-----------
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 +++----
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2 files changed, 34 insertions(+), 33 deletions(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -19,7 +19,8 @@
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#include <bcm63xx_io.h>
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#include <bcm63xx_irq.h>
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-static u32 irq_stat_addr, irq_mask_addr;
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+static u32 irq_stat_addr[2];
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+static u32 irq_mask_addr[2];
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static void (*dispatch_internal)(void);
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static int is_ext_irq_cascaded;
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static unsigned int ext_irq_count;
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@@ -64,8 +65,8 @@ void __dispatch_internal_##width(void)
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for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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u32 val; \
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\
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- val = bcm_readl(irq_stat_addr + src * sizeof(u32)); \
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- val &= bcm_readl(irq_mask_addr + src * sizeof(u32)); \
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+ val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \
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+ val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
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pending[--tgt] = val; \
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\
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if (val) \
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@@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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\
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- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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+ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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val &= ~(1 << bit); \
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- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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+ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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} \
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\
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static void __internal_irq_unmask_##width(unsigned int irq) \
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@@ -103,9 +104,9 @@ static void __internal_irq_unmask_##widt
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unsigned reg = (irq / 32) ^ (width/32 - 1); \
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unsigned bit = irq & 0x1f; \
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\
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- val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
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+ val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
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val |= (1 << bit); \
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- bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
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+ bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
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}
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BUILD_IPIC_INTERNAL(32);
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@@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void)
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{
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int irq_bits;
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- irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
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- irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
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+ irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
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+ irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
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switch (bcm63xx_get_cpu_id()) {
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case BCM3368_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_3368_REG;
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- irq_mask_addr += PERF_IRQMASK_3368_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
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+ irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
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break;
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case BCM6328_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6328_REG;
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- irq_mask_addr += PERF_IRQMASK_6328_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
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+ irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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@@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void)
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
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break;
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case BCM6338_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6338_REG;
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- irq_mask_addr += PERF_IRQMASK_6338_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
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+ irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
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break;
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case BCM6345_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6345_REG;
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- irq_mask_addr += PERF_IRQMASK_6345_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
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+ irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
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break;
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case BCM6348_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6348_REG;
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- irq_mask_addr += PERF_IRQMASK_6348_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
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+ irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
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irq_bits = 32;
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ext_irq_count = 4;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
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break;
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case BCM6358_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6358_REG;
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- irq_mask_addr += PERF_IRQMASK_6358_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
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+ irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
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irq_bits = 32;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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@@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void)
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
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break;
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case BCM6362_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6362_REG;
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- irq_mask_addr += PERF_IRQMASK_6362_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
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+ irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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@@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void)
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
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break;
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case BCM6368_CPU_ID:
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- irq_stat_addr += PERF_IRQSTAT_6368_REG;
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- irq_mask_addr += PERF_IRQMASK_6368_REG;
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+ irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
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+ irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
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irq_bits = 64;
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ext_irq_count = 6;
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is_ext_irq_cascaded = 1;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -215,23 +215,23 @@
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/* Interrupt Mask register */
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#define PERF_IRQMASK_3368_REG 0xc
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-#define PERF_IRQMASK_6328_REG 0x20
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+#define PERF_IRQMASK_6328_REG(x) (0x20 + (x) * 0x10)
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#define PERF_IRQMASK_6338_REG 0xc
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#define PERF_IRQMASK_6345_REG 0xc
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#define PERF_IRQMASK_6348_REG 0xc
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-#define PERF_IRQMASK_6358_REG 0xc
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-#define PERF_IRQMASK_6362_REG 0x20
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-#define PERF_IRQMASK_6368_REG 0x20
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+#define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
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+#define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
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+#define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
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/* Interrupt Status register */
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#define PERF_IRQSTAT_3368_REG 0x10
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-#define PERF_IRQSTAT_6328_REG 0x28
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+#define PERF_IRQSTAT_6328_REG(x) (0x28 + (x) * 0x10)
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#define PERF_IRQSTAT_6338_REG 0x10
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#define PERF_IRQSTAT_6345_REG 0x10
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#define PERF_IRQSTAT_6348_REG 0x10
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-#define PERF_IRQSTAT_6358_REG 0x10
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-#define PERF_IRQSTAT_6362_REG 0x28
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-#define PERF_IRQSTAT_6368_REG 0x28
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+#define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
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+#define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
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+#define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
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/* External Interrupt Configuration register */
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#define PERF_EXTIRQ_CFG_REG_3368 0x14
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