a4c0645326
Thank you Peter Wagner for the patch. I refreshed the kernel patches and added the md5sum of the kernel. SVN-Revision: 26905
286 lines
8.7 KiB
Diff
286 lines
8.7 KiB
Diff
--- a/drivers/i2c/busses/Kconfig
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+++ b/drivers/i2c/busses/Kconfig
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@@ -283,7 +283,7 @@ comment "I2C system bus drivers (mostly
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config I2C_AT91
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tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
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- depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
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+ depends on ARCH_AT91 && EXPERIMENTAL
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help
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This supports the use of the I2C interface on Atmel AT91
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processors.
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--- a/drivers/i2c/busses/i2c-at91.c
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+++ b/drivers/i2c/busses/i2c-at91.c
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@@ -11,8 +11,18 @@
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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+
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+ D. Gilbert [20100318 AT91SAM9G20]
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+ - Check for NACK, a NACK will abort current tranfser,
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+ returned as errno=EREMOTEIO unless I2C_M_IGNORE_NAK is set
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+ - Only supports 7 bit I2C device (slave) address
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+ - clockrate adjustable (module_param).
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*/
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+
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+/* Uncomment following line to see dev_dbg() output in logs */
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+/* #define DEBUG 1 */
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+
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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@@ -32,26 +42,28 @@
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#define TWI_CLOCK 100000 /* Hz. max 400 Kbits/sec */
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+static unsigned int clockrate = TWI_CLOCK;
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+static unsigned int prev_clockrate = TWI_CLOCK;
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static struct clk *twi_clk;
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static void __iomem *twi_base;
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#define at91_twi_read(reg) __raw_readl(twi_base + (reg))
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#define at91_twi_write(reg, val) __raw_writel((val), twi_base + (reg))
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-
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/*
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- * Initialize the TWI hardware registers.
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+ * Set TWI clock dividers based on clockrate (clock rate for SCL)
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*/
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-static void __devinit at91_twi_hwinit(void)
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+static void at91_twi_clock_dividers(void)
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{
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unsigned long cdiv, ckdiv;
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- at91_twi_write(AT91_TWI_IDR, 0xffffffff); /* Disable all interrupts */
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- at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST); /* Reset peripheral */
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- at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN); /* Set Master mode */
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+ if (clockrate < 1000)
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+ clockrate = 1000;
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+ else if (clockrate > 400000)
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+ clockrate = 400000;
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- /* Calcuate clock dividers */
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- cdiv = (clk_get_rate(twi_clk) / (2 * TWI_CLOCK)) - 3;
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+ /* Calculate clock dividers */
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+ cdiv = (clk_get_rate(twi_clk) / (2 * clockrate)) - 3;
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cdiv = cdiv + 1; /* round up */
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ckdiv = 0;
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while (cdiv > 255) {
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@@ -61,41 +73,92 @@ static void __devinit at91_twi_hwinit(vo
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if (cpu_is_at91rm9200()) { /* AT91RM9200 Errata #22 */
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if (ckdiv > 5) {
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- printk(KERN_ERR "AT91 I2C: Invalid TWI_CLOCK value!\n");
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+ printk(KERN_ERR "i2c-at91: Invalid AT91RM9200 clock rate\n");
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ckdiv = 5;
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}
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}
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+ /* AT91SAM9G20 has 3 bits for ckdiv so it cannot exceed 7 */
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+ if (cpu_is_at91sam9g20()) {
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+ if (ckdiv > 7) {
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+ printk(KERN_ERR "i2c-at91: Invalid AT91SAM9G20 clock "
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+ "rate, ckdiv=%lu\n", ckdiv);
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+ ckdiv = 7;
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+ }
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+ }
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at91_twi_write(AT91_TWI_CWGR, (ckdiv << 16) | (cdiv << 8) | cdiv);
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+ prev_clockrate = clockrate;
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}
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/*
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- * Poll the i2c status register until the specified bit is set.
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- * Returns 0 if timed out (100 msec).
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+ * Initialize the TWI hardware registers.
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*/
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-static short at91_poll_status(unsigned long bit)
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+static void __devinit at91_twi_hwinit(void)
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{
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- int loop_cntr = 10000;
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+ at91_twi_write(AT91_TWI_IDR, 0xffffffff); /* Disable all interrupts */
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+ at91_twi_write(AT91_TWI_CR, AT91_TWI_SWRST); /* Reset peripheral */
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+ /* Set Master mode; Atmel suggests disabling slave mode */
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+ at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN | AT91_TWI_SVDIS);
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+ at91_twi_clock_dividers();
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+}
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+
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+/*
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+ * Poll the i2c status register until the specified bit is set or a NACK
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+ * occurs. Returns 0 if timed out (50 msec). If nack_seen_p is non-NULL
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+ * then write 0 to it first, then if the NACK bit is set in the status
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+ * register then write 1 to it and immediately return with a value of 1.
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+ */
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+static short at91_poll_status(unsigned long bit, int * nack_seen_p)
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+{
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+ int loop_cntr = 5000;
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+ unsigned long stat;
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+
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+ if (nack_seen_p)
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+ *nack_seen_p = 0;
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+ if (clockrate <= 20000)
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+ loop_cntr = 100;
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do {
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- udelay(10);
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- } while (!(at91_twi_read(AT91_TWI_SR) & bit) && (--loop_cntr > 0));
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+ if (clockrate <= 20000)
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+ udelay(100);
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+ else if (clockrate <= 100000)
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+ udelay(10);
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+ else
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+ udelay(3);
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+ stat = at91_twi_read(AT91_TWI_SR);
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+ if ((stat & AT91_TWI_NACK) && nack_seen_p) {
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+ *nack_seen_p = 1;
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+ return 1;
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+ }
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+ } while (!(stat & bit) && (--loop_cntr > 0));
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return (loop_cntr > 0);
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}
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static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length)
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{
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+ int nack_seen = 0;
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+ int sent_stop = 0;
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+
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/* Send Start */
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- at91_twi_write(AT91_TWI_CR, AT91_TWI_START);
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+ if (1 == length) {
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+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START | AT91_TWI_STOP);
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+ sent_stop = 1;
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+ } else
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+ at91_twi_write(AT91_TWI_CR, AT91_TWI_START);
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/* Read data */
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while (length--) {
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- if (!length) /* need to send Stop before reading last byte */
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+ /* send Stop before reading last byte (if not already done) */
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+ if ((0 == length) && (0 == sent_stop))
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at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP);
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- if (!at91_poll_status(AT91_TWI_RXRDY)) {
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+ if (!at91_poll_status(AT91_TWI_RXRDY, &nack_seen)) {
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dev_dbg(&adap->dev, "RXRDY timeout\n");
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return -ETIMEDOUT;
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+ } else if (nack_seen) {
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+ dev_dbg(&adap->dev, "read NACKed\n");
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+ /* NACK supplies Stop */
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+ return -EREMOTEIO;
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}
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*buf++ = (at91_twi_read(AT91_TWI_RHR) & 0xff);
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}
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@@ -105,16 +168,24 @@ static int xfer_read(struct i2c_adapter
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static int xfer_write(struct i2c_adapter *adap, unsigned char *buf, int length)
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{
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+ int nack_seen = 0;
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+
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/* Load first byte into transmitter */
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at91_twi_write(AT91_TWI_THR, *buf++);
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- /* Send Start */
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+ /* Send Start [AT91SAM9G20 does not need this on write] */
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at91_twi_write(AT91_TWI_CR, AT91_TWI_START);
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do {
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- if (!at91_poll_status(AT91_TWI_TXRDY)) {
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+ if (!at91_poll_status(AT91_TWI_TXRDY, &nack_seen)) {
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dev_dbg(&adap->dev, "TXRDY timeout\n");
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+ /* Set Master mode again */
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+ at91_twi_write(AT91_TWI_CR, AT91_TWI_MSEN);
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return -ETIMEDOUT;
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+ } else if (nack_seen) {
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+ dev_dbg(&adap->dev, "write NACKed\n");
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+ /* NACK supplies Stop */
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+ return -EREMOTEIO;
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}
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length--; /* byte was transmitted */
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@@ -123,7 +194,7 @@ static int xfer_write(struct i2c_adapter
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at91_twi_write(AT91_TWI_THR, *buf++);
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} while (length);
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- /* Send Stop */
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+ /* Send Stop [AT91SAM9G20 does not need this on write] */
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at91_twi_write(AT91_TWI_CR, AT91_TWI_STOP);
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return 0;
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@@ -136,11 +207,19 @@ static int xfer_write(struct i2c_adapter
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* Instead the "internal device address" has to be written using a separate
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* i2c message.
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* http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html
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+ * [dpg] By 2010 silicon bugs should be fixed, will need IADR for 10 bit device address
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*/
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static int at91_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
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{
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int i, ret;
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+ int nack_seen = 0;
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+ if (prev_clockrate != clockrate) {
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+ dev_dbg(&adap->dev, "at91_xfer: prev_clockrate=%u "
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+ "clockrate=%u, change\n", prev_clockrate, clockrate);
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+ at91_twi_clock_dividers();
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+ msleep(1); /* let things settle */
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+ }
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dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
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for (i = 0; i < num; i++) {
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@@ -158,13 +237,23 @@ static int at91_xfer(struct i2c_adapter
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else
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ret = xfer_write(adap, pmsg->buf, pmsg->len);
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- if (ret)
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- return ret;
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-
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+ if (ret) {
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+ if ((I2C_M_IGNORE_NAK & pmsg->flags) &&
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+ (-EREMOTEIO == ret)) {
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+ dev_dbg(&adap->dev, "transfer "
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+ "NACKed, skip to next\n");
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+ pmsg++;
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+ continue;
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+ } else
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+ return ret;
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+ }
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/* Wait until transfer is finished */
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- if (!at91_poll_status(AT91_TWI_TXCOMP)) {
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+ if (!at91_poll_status(AT91_TWI_TXCOMP, &nack_seen)) {
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dev_dbg(&adap->dev, "TXCOMP timeout\n");
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return -ETIMEDOUT;
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+ } else if (nack_seen) {
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+ dev_dbg(&adap->dev, "TXCOMP NACKed\n");
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+ return -EREMOTEIO;
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}
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}
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dev_dbg(&adap->dev, "transfer complete\n");
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@@ -239,7 +328,8 @@ static int __devinit at91_i2c_probe(stru
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goto fail3;
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}
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- dev_info(&pdev->dev, "AT91 i2c bus driver.\n");
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+ dev_info(&pdev->dev, "AT91 TWI (I2C) bus driver [SCL %d Hz]\n",
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+ clockrate);
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return 0;
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fail3:
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@@ -295,6 +385,11 @@ static int at91_i2c_resume(struct platfo
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#define at91_i2c_resume NULL
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#endif
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+/* I2C clock speed, in Hz 0-400kHz*/
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+module_param(clockrate, uint, S_IRUGO | S_IWUSR);
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+MODULE_PARM_DESC(clockrate,
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+ "SCL clock rate, 1000 to 400000 Hz (def: 100 kHz)");
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+
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/* work with "modprobe at91_i2c" from hotplugging or coldplugging */
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MODULE_ALIAS("platform:at91_i2c");
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@@ -323,5 +418,5 @@ module_init(at91_i2c_init);
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module_exit(at91_i2c_exit);
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MODULE_AUTHOR("Rick Bronson");
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-MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
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+MODULE_DESCRIPTION("I2C (TWI) master driver for Atmel AT91");
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MODULE_LICENSE("GPL");
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