309 lines
8.8 KiB
Diff
309 lines
8.8 KiB
Diff
From 580d6aef484b22b5da88588d9a2d944b4f06dc98 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 20 Mar 2012 08:26:04 +0100
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Subject: [PATCH 57/70] MIPS: clean up clock code
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---
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arch/mips/lantiq/clk.c | 11 +++
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arch/mips/lantiq/clk.h | 3 +-
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arch/mips/lantiq/xway/devices.c | 2 +-
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arch/mips/lantiq/xway/sysctrl.c | 166 ++++++++++++++++++++++++++++++---------
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4 files changed, 143 insertions(+), 39 deletions(-)
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--- a/arch/mips/lantiq/clk.c
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+++ b/arch/mips/lantiq/clk.c
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@@ -44,6 +44,7 @@ struct clk *clk_get_fpi(void)
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{
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return &cpu_clk_generic[1];
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}
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+EXPORT_SYMBOL_GPL(clk_get_fpi);
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struct clk *clk_get_io(void)
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{
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@@ -70,6 +71,16 @@ unsigned long clk_get_rate(struct clk *c
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}
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EXPORT_SYMBOL(clk_get_rate);
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+int clk_set_rate(struct clk *clk, unsigned long rate)
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+{
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+ if (unlikely(!clk_good(clk)))
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+ return 0;
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+
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+ clk->rate = rate;
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+ return 0;
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+}
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+EXPORT_SYMBOL(clk_set_rate);
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+
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int clk_enable(struct clk *clk)
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{
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if (unlikely(!clk_good(clk)))
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--- a/arch/mips/lantiq/clk.h
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+++ b/arch/mips/lantiq/clk.h
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@@ -12,6 +12,7 @@
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#include <linux/clkdev.h>
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/* clock speeds */
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+#define CLOCK_33M 33333333
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#define CLOCK_60M 60000000
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#define CLOCK_62_5M 62500000
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#define CLOCK_83M 83333333
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@@ -38,9 +39,9 @@
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struct clk {
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struct clk_lookup cl;
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unsigned long rate;
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- unsigned long (*get_rate) (void);
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unsigned int module;
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unsigned int bits;
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+ unsigned long (*get_rate) (void);
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int (*enable) (struct clk *clk);
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void (*disable) (struct clk *clk);
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int (*activate) (struct clk *clk);
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--- a/arch/mips/lantiq/xway/devices.c
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+++ b/arch/mips/lantiq/xway/devices.c
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@@ -59,7 +59,7 @@ static struct resource ltq_stp_resource
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void __init ltq_register_gpio_stp(void)
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{
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- platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1);
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+ platform_device_register_simple("ltq_stp", -1, <q_stp_resource, 1);
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}
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/* asc ports - amazon se has its own serial mapping */
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -16,40 +16,57 @@
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#include "../devices.h"
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/* clock control register */
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-#define LTQ_CGU_IFCCR 0x0018
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+#define CGU_IFCCR 0x0018
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/* system clock register */
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-#define LTQ_CGU_SYS 0x0010
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-
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-/* the enable / disable registers */
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-#define LTQ_PMU_PWDCR 0x1C
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-#define LTQ_PMU_PWDSR 0x20
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-#define LTQ_PMU_PWDCR1 0x24
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-#define LTQ_PMU_PWDSR1 0x28
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-
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-#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR))
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-#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR))
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-
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-/* CGU - clock generation unit */
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-#define CGU_EPHY 0x10
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+#define CGU_SYS 0x0010
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+/* pci control register */
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+#define CGU_PCICR 0x0034
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+/* ephy configuration register */
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+#define CGU_EPHY 0x10
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+/* power control register */
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+#define PMU_PWDCR 0x1C
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+/* power status register */
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+#define PMU_PWDSR 0x20
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+/* power control register */
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+#define PMU_PWDCR1 0x24
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+/* power status register */
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+#define PMU_PWDSR1 0x28
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+/* power control register */
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+#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
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+/* power status register */
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+#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
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/* PMU - power management unit */
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-#define PMU_DMA 0x0020
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-#define PMU_SPI 0x0100
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-#define PMU_EPHY 0x0080
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-#define PMU_USB 0x8041
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-#define PMU_STP 0x0800
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-#define PMU_GPT 0x1000
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-#define PMU_PPE 0x2000
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-#define PMU_FPI 0x4000
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-#define PMU_SWITCH 0x10000000
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-#define PMU_AHBS 0x2000
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-#define PMU_AHBM 0x8000
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-#define PMU_PCIE_CLK 0x80000000
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-
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-#define PMU1_PCIE_PHY 0x0001
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-#define PMU1_PCIE_CTL 0x0002
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-#define PMU1_PCIE_MSI 0x0020
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-#define PMU1_PCIE_PDI 0x0010
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+#define PMU_USB0_P BIT(0)
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+#define PMU_PCI BIT(4)
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+#define PMU_DMA BIT(5)
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+#define PMU_USB0 BIT(5)
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+#define PMU_SPI BIT(8)
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+#define PMU_EPHY BIT(7)
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+#define PMU_EBU BIT(10)
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+#define PMU_STP BIT(11)
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+#define PMU_GPT BIT(12)
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+#define PMU_PPE BIT(13)
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+#define PMU_AHBS BIT(13) /* vr9 */
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+#define PMU_FPI BIT(14)
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+#define PMU_AHBM BIT(15)
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+#define PMU_PPE_QSB BIT(18)
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+#define PMU_PPE_SLL01 BIT(19)
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+#define PMU_PPE_TC BIT(21)
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+#define PMU_PPE_EMA BIT(22)
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+#define PMU_PPE_DPLUM BIT(23)
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+#define PMU_PPE_DPLUS BIT(24)
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+#define PMU_USB1_P BIT(26)
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+#define PMU_USB1 BIT(27)
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+#define PMU_SWITCH BIT(28)
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+#define PMU_PPE_TOP BIT(29)
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+#define PMU_GPHY BIT(30)
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+#define PMU_PCIE_CLK BIT(31)
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+
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+#define PMU1_PCIE_PHY BIT(0)
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+#define PMU1_PCIE_CTL BIT(1)
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+#define PMU1_PCIE_PDI BIT(4)
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+#define PMU1_PCIE_MSI BIT(5)
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#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
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#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
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@@ -69,13 +86,13 @@ static void __iomem *ltq_pmu_membase;
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static int ltq_cgu_enable(struct clk *clk)
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{
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- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR);
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+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
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return 0;
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}
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static void ltq_cgu_disable(struct clk *clk)
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{
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- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR);
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+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
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}
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static int ltq_pmu_enable(struct clk *clk)
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@@ -94,9 +111,49 @@ static int ltq_pmu_enable(struct clk *cl
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static void ltq_pmu_disable(struct clk *clk)
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{
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- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR);
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+ ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits,
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+ PWDCR(clk->module));
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}
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+static int ltq_pci_enable(struct clk *clk)
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+{
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+ unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
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+ /* set clock bus speed */
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+ if (ltq_is_ar9()) {
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+ ifccr &= ~0x1f00000;
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+ if (clk->rate == CLOCK_33M)
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+ ifccr |= 0xe00000;
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+ else
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+ ifccr |= 0x700000; /* 62.5M */
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+ } else {
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+ ifccr &= ~0xf00000;
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+ if (clk->rate == CLOCK_33M)
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+ ifccr |= 0x800000;
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+ else
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+ ifccr |= 0x400000; /* 62.5M */
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+ }
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+ ltq_cgu_w32(ifccr, CGU_IFCCR);
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+ return 0;
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+}
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+
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+static int ltq_pci_ext_enable(struct clk *clk)
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+{
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+ /* enable external pci clock */
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+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
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+ CGU_IFCCR);
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+ ltq_cgu_w32((1 << 30), CGU_PCICR);
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+ return 0;
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+}
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+
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+static void ltq_pci_ext_disable(struct clk *clk)
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+{
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+ /* enable external pci clock */
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+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
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+ CGU_IFCCR);
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+ ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
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+}
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+
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+/* manage the clock gates via PMU */
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static inline void clkdev_add_pmu(const char *dev, const char *con,
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unsigned int module, unsigned int bits)
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{
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@@ -112,6 +169,7 @@ static inline void clkdev_add_pmu(const
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clkdev_add(&clk->cl);
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}
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+/* manage the clock generator */
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static inline void clkdev_add_cgu(const char *dev, const char *con,
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unsigned int bits)
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{
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@@ -126,6 +184,33 @@ static inline void clkdev_add_cgu(const
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clkdev_add(&clk->cl);
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}
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+/* pci needs its own enable function */
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+static inline void clkdev_add_pci(void)
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+{
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+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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+ struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
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+
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+ /* main pci clock */
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+ clk->cl.dev_id = "ltq_pci";
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+ clk->cl.con_id = NULL;
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+ clk->cl.clk = clk;
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+ clk->rate = CLOCK_33M;
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+ clk->enable = ltq_pci_enable;
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+ clk->disable = ltq_pmu_disable;
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+ clk->module = 0;
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+ clk->bits = PMU_PCI;
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+ clkdev_add(&clk->cl);
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+
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+ /* use internal/external bus clock */
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+ clk_ext->cl.dev_id = "ltq_pci";
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+ clk_ext->cl.con_id = "external";
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+ clk_ext->cl.clk = clk_ext;
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+ clk_ext->enable = ltq_pci_ext_enable;
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+ clk_ext->disable = ltq_pci_ext_disable;
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+ clkdev_add(&clk_ext->cl);
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+
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+}
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+
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void __init ltq_soc_init(void)
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{
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ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource);
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@@ -144,14 +229,16 @@ void __init ltq_soc_init(void)
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
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/* add our clocks */
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+ clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI);
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clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA);
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clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP);
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clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI);
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clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT);
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+ clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU);
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if (!ltq_is_vr9())
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clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE);
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if (ltq_is_ase()) {
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- if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
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+ if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
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clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
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else
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clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
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@@ -166,11 +253,16 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI);
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clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL);
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clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
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- clkdev_add_pmu("usb0", NULL, 0, (1<<6) | 1);
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- clkdev_add_pmu("usb1", NULL, 0, (1<<26) | (1<<27));
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+ clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P);
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+ clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P);
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+ clkdev_add_pmu("ltq_vrx200", NULL, 0,
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+ PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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+ PMU_PPE_QSB);
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} else {
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clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
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ltq_danube_io_region_clock());
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+ clkdev_add_pci();
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if (ltq_is_ar9())
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clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH);
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}
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