150 lines
4.2 KiB
Diff
150 lines
4.2 KiB
Diff
From 11e7ff129807394d87c937b880bb58972dc91fc0 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Thu, 28 Nov 2013 09:00:47 -0300
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Subject: [PATCH] fixup! clk: sunxi: add PLL5 and PLL6 support
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---
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drivers/clk/sunxi/clk-sunxi.c | 83 +++++++++++++++++++++++++++++++++++--------
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1 file changed, 69 insertions(+), 14 deletions(-)
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index d2b8d3c..3ce33b8 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -807,10 +807,11 @@ struct divs_data {
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struct clk_div_table *table; /* is it a table based divisor? */
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u8 shift; /* otherwise it's a normal divisor with this shift */
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u8 pow; /* is it power-of-two based? */
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+ u8 gate; /* is it independently gateable? */
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} div[SUNXI_DIVS_MAX_QTY];
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};
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-static struct clk_div_table pll6_sata_table[] = {
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+static struct clk_div_table pll6_sata_tbl[] = {
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{ .val = 0, .div = 6, },
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{ .val = 1, .div = 12, },
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{ .val = 2, .div = 18, },
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@@ -829,7 +830,7 @@ struct divs_data {
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static const struct divs_data pll6_divs_data __initconst = {
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.factors = &sun4i_pll5_data,
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.div = {
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- { .shift = 0, .table = pll6_sata_table }, /* M, SATA */
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+ { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
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{ .fixed = 2 }, /* P, other */
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}
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};
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@@ -852,6 +853,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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const char *parent = node->name;
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const char *clk_name;
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struct clk **clks, *pclk;
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+ struct clk_hw *gate_hw, *rate_hw;
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+ const struct clk_ops *rate_ops;
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+ struct clk_gate *gate = NULL;
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+ struct clk_fixed_factor *fix_factor;
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+ struct clk_divider *divider;
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void *reg;
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int i = 0;
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int flags, clkflags;
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@@ -866,10 +872,9 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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return;
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clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
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- if (!clks) {
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- kfree(clk_data);
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- return;
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- }
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+ if (!clks)
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+ goto free_clkdata;
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+
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clk_data->clks = clks;
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/* It's not a good idea to have automatic reparenting changing
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@@ -881,19 +886,60 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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i, &clk_name) != 0)
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break;
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+ gate_hw = NULL;
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+ rate_hw = NULL;
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+ rate_ops = NULL;
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+
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+ /* If this leaf clock can be gated, create a gate */
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+ if (data->div[i].gate) {
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+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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+ if (!gate)
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+ goto free_clks;
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+
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+ gate->reg = reg;
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+ gate->bit_idx = data->div[i].gate;
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+ gate->lock = &clk_lock;
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+
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+ gate_hw = &gate->hw;
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+ }
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+
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+ /* Leaves can be fixed or configurable divisors */
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if (data->div[i].fixed) {
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- clks[i] = clk_register_fixed_factor(NULL, clk_name,
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- parent, clkflags,
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- 1, data->div[i].fixed);
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+ fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
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+ if (!fix_factor)
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+ goto free_gate;
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+
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+ fix_factor->mult = 1;
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+ fix_factor->div = data->div[i].fixed;
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+
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+ rate_hw = &fix_factor->hw;
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+ rate_ops = &clk_fixed_factor_ops;
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} else {
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+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
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+ if (!divider)
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+ goto free_gate;
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+
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flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
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- clks[i] = clk_register_divider_table(NULL, clk_name,
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- parent, clkflags, reg,
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- data->div[i].shift,
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- SUNXI_DIVISOR_WIDTH, flags,
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- data->div[i].table, &clk_lock);
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+
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+ divider->reg = reg;
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+ divider->shift = data->div[i].shift;
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+ divider->width = SUNXI_DIVISOR_WIDTH;
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+ divider->flags = flags;
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+ divider->lock = &clk_lock;
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+ divider->table = data->div[i].table;
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+
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+ rate_hw = ÷r->hw;
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+ rate_ops = &clk_divider_ops;
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}
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+ /* Wrap the (potential) gate and the divisor on a composite
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+ * clock to unify them */
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+ clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
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+ NULL, NULL,
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+ rate_hw, rate_ops,
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+ gate_hw, &clk_gate_ops,
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+ clkflags);
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+
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WARN_ON(IS_ERR(clk_data->clks[i]));
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clk_register_clkdev(clks[i], clk_name, NULL);
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}
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@@ -905,6 +951,15 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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clk_data->clk_num = i;
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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+
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+ return;
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+
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+free_gate:
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+ kfree(gate);
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+free_clks:
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+ kfree(clks);
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+free_clkdata:
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+ kfree(clk_data);
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}
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--
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1.8.5.1
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