227 lines
6.7 KiB
Diff
227 lines
6.7 KiB
Diff
From ed56e6322b067a898a25bda1774eb1180a832246 Mon Sep 17 00:00:00 2001
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From: Andy Gross <andy.gross@linaro.org>
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Date: Tue, 2 Feb 2016 17:00:53 -0600
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Subject: [PATCH] spi: qup: Fix DMA mode to work correctly
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This patch fixes a few issues with the DMA mode. The QUP needs to be
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placed in the run mode before the DMA transactions are executed. The
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conditions for being able to DMA vary between revisions of the QUP.
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This is due to v1.1.1 using ADM DMA and later revisions using BAM.
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Change-Id: Ib1f876eaa05d079e0bca4358d2b25b2940986089
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Signed-off-by: Andy Gross <andy.gross@linaro.org>
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---
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drivers/spi/spi-qup.c | 95 ++++++++++++++++++++++++++++++++++-----------------
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1 file changed, 63 insertions(+), 32 deletions(-)
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diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c
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index fe629f2..089c5e8 100644
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--- a/drivers/spi/spi-qup.c
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+++ b/drivers/spi/spi-qup.c
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@@ -143,6 +143,7 @@ struct spi_qup {
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struct spi_transfer *xfer;
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struct completion done;
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+ struct completion dma_tx_done;
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int error;
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int w_size; /* bytes per SPI word */
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int n_words;
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@@ -285,16 +286,16 @@ static void spi_qup_fifo_write(struct spi_qup *controller,
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static void spi_qup_dma_done(void *data)
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{
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- struct spi_qup *qup = data;
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+ struct completion *done = data;
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- complete(&qup->done);
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+ complete(done);
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}
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static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
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enum dma_transfer_direction dir,
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- dma_async_tx_callback callback)
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+ dma_async_tx_callback callback,
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+ void *data)
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{
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- struct spi_qup *qup = spi_master_get_devdata(master);
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unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
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struct dma_async_tx_descriptor *desc;
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struct scatterlist *sgl;
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@@ -313,11 +314,11 @@ static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
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}
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desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
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- if (!desc)
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- return -EINVAL;
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+ if (IS_ERR_OR_NULL(desc))
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+ return desc ? PTR_ERR(desc) : -EINVAL;
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desc->callback = callback;
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- desc->callback_param = qup;
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+ desc->callback_param = data;
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cookie = dmaengine_submit(desc);
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@@ -333,18 +334,29 @@ static void spi_qup_dma_terminate(struct spi_master *master,
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dmaengine_terminate_all(master->dma_rx);
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}
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-static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
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+static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer,
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+unsigned long timeout)
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{
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+ struct spi_qup *qup = spi_master_get_devdata(master);
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dma_async_tx_callback rx_done = NULL, tx_done = NULL;
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int ret;
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+ /* before issuing the descriptors, set the QUP to run */
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+ ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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+ if (ret) {
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+ dev_warn(qup->dev, "cannot set RUN state\n");
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+ return ret;
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+ }
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+
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if (xfer->rx_buf)
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rx_done = spi_qup_dma_done;
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- else if (xfer->tx_buf)
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+
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+ if (xfer->tx_buf)
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tx_done = spi_qup_dma_done;
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if (xfer->rx_buf) {
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- ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done);
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+ ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done,
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+ &qup->done);
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if (ret)
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return ret;
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@@ -352,17 +364,26 @@ static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
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}
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if (xfer->tx_buf) {
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- ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done);
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+ ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done,
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+ &qup->dma_tx_done);
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if (ret)
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return ret;
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dma_async_issue_pending(master->dma_tx);
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}
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- return 0;
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+ if (xfer->rx_buf && !wait_for_completion_timeout(&qup->done, timeout))
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+ return -ETIMEDOUT;
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+
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+ if (xfer->tx_buf &&
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+ !wait_for_completion_timeout(&qup->dma_tx_done, timeout))
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+ ret = -ETIMEDOUT;
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+
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+ return ret;
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}
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-static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
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+static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer,
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+ unsigned long timeout)
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{
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struct spi_qup *qup = spi_master_get_devdata(master);
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int ret;
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@@ -382,6 +403,15 @@ static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
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if (qup->mode == QUP_IO_M_MODE_FIFO)
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spi_qup_fifo_write(qup, xfer);
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+ ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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+ if (ret) {
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+ dev_warn(qup->dev, "cannot set RUN state\n");
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+ return ret;
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+ }
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+
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+ if (!wait_for_completion_timeout(&qup->done, timeout))
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+ return -ETIMEDOUT;
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+
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return 0;
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}
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@@ -430,7 +460,6 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
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dev_warn(controller->dev, "CLK_OVER_RUN\n");
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if (spi_err & SPI_ERROR_CLK_UNDER_RUN)
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dev_warn(controller->dev, "CLK_UNDER_RUN\n");
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-
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error = -EIO;
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}
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@@ -619,6 +648,7 @@ static int spi_qup_transfer_one(struct spi_master *master,
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timeout = 100 * msecs_to_jiffies(timeout);
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reinit_completion(&controller->done);
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+ reinit_completion(&controller->dma_tx_done);
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spin_lock_irqsave(&controller->lock, flags);
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controller->xfer = xfer;
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@@ -628,21 +658,13 @@ static int spi_qup_transfer_one(struct spi_master *master,
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spin_unlock_irqrestore(&controller->lock, flags);
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if (spi_qup_is_dma_xfer(controller->mode))
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- ret = spi_qup_do_dma(master, xfer);
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+ ret = spi_qup_do_dma(master, xfer, timeout);
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else
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- ret = spi_qup_do_pio(master, xfer);
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+ ret = spi_qup_do_pio(master, xfer, timeout);
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if (ret)
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goto exit;
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- if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
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- dev_warn(controller->dev, "cannot set EXECUTE state\n");
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- goto exit;
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- }
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-
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- if (!wait_for_completion_timeout(&controller->done, timeout))
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- ret = -ETIMEDOUT;
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-
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exit:
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spi_qup_set_state(controller, QUP_STATE_RESET);
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spin_lock_irqsave(&controller->lock, flags);
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@@ -664,15 +686,23 @@ static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
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size_t dma_align = dma_get_cache_alignment();
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int n_words;
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- if (xfer->rx_buf && (xfer->len % qup->in_blk_sz ||
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- IS_ERR_OR_NULL(master->dma_rx) ||
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- !IS_ALIGNED((size_t)xfer->rx_buf, dma_align)))
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- return false;
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+ if (xfer->rx_buf) {
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+ if (!IS_ALIGNED((size_t)xfer->rx_buf, dma_align) ||
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+ IS_ERR_OR_NULL(master->dma_rx))
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+ return false;
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- if (xfer->tx_buf && (xfer->len % qup->out_blk_sz ||
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- IS_ERR_OR_NULL(master->dma_tx) ||
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- !IS_ALIGNED((size_t)xfer->tx_buf, dma_align)))
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- return false;
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+ if (qup->qup_v1 && (xfer->len % qup->in_blk_sz))
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+ return false;
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+ }
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+
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+ if (xfer->tx_buf) {
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+ if (!IS_ALIGNED((size_t)xfer->tx_buf, dma_align) ||
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+ IS_ERR_OR_NULL(master->dma_tx))
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+ return false;
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+
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+ if (qup->qup_v1 && (xfer->len % qup->out_blk_sz))
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+ return false;
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+ }
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n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
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if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
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@@ -875,6 +905,7 @@ static int spi_qup_probe(struct platform_device *pdev)
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spin_lock_init(&controller->lock);
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init_completion(&controller->done);
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+ init_completion(&controller->dma_tx_done);
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iomode = readl_relaxed(base + QUP_IO_M_MODES);
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--
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2.7.2
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