175 lines
4.4 KiB
C
175 lines
4.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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*/
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/*
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* Platform devices for Atheros SoCs
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include "../ar531x.h"
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/*
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* Called when an interrupt is received, this function
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* determines exactly which interrupt it was, and it
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* invokes the appropriate handler.
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*
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* Implicitly, we also define interrupt priority by
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* choosing which to dispatch first.
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*/
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asmlinkage void ar5312_irq_dispatch(void)
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{
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int pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP2)
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do_IRQ(AR5312_IRQ_WLAN0_INTRS);
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else if (pending & CAUSEF_IP3)
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do_IRQ(AR5312_IRQ_ENET0_INTRS);
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else if (pending & CAUSEF_IP4)
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do_IRQ(AR5312_IRQ_ENET1_INTRS);
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else if (pending & CAUSEF_IP5)
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do_IRQ(AR5312_IRQ_WLAN1_INTRS);
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else if (pending & CAUSEF_IP6) {
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unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
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if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
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do_IRQ(AR531X_MISC_IRQ_TIMER);
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(void)sysRegRead(AR531X_TIMER);
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} else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
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do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
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else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
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do_IRQ(AR531X_MISC_IRQ_UART0);
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else if (ar531x_misc_intrs & AR531X_ISR_WD)
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do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
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else
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do_IRQ(AR531X_MISC_IRQ_NONE);
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} else if (pending & CAUSEF_IP7) {
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do_IRQ(AR531X_IRQ_CPU_CLOCK);
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}
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else
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do_IRQ(AR531X_IRQ_NONE);
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}
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/* Enable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5312_misc_intr_enable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR531X_IMR);
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imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
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sysRegWrite(AR531X_IMR, imr);
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sysRegRead(AR531X_IMR); /* flush write buffer */
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}
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/* Disable the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5312_misc_intr_disable(unsigned int irq)
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{
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unsigned int imr;
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imr = sysRegRead(AR531X_IMR);
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imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
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sysRegWrite(AR531X_IMR, imr);
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sysRegRead(AR531X_IMR); /* flush write buffer */
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}
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/* Turn on the specified AR531X_MISC_IRQ interrupt */
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static unsigned int
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ar5312_misc_intr_startup(unsigned int irq)
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{
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ar5312_misc_intr_enable(irq);
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return 0;
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}
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/* Turn off the specified AR531X_MISC_IRQ interrupt */
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static void
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ar5312_misc_intr_shutdown(unsigned int irq)
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{
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ar5312_misc_intr_disable(irq);
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}
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static void
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ar5312_misc_intr_ack(unsigned int irq)
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{
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ar5312_misc_intr_disable(irq);
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}
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static void
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ar5312_misc_intr_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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ar5312_misc_intr_enable(irq);
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}
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static struct irq_chip ar5312_misc_intr_controller = {
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.typename = "AR5312 misc",
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.startup = ar5312_misc_intr_startup,
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.shutdown = ar5312_misc_intr_shutdown,
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.enable = ar5312_misc_intr_enable,
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.disable = ar5312_misc_intr_disable,
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.ack = ar5312_misc_intr_ack,
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.end = ar5312_misc_intr_end,
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};
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static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
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{
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u32 proc1 = sysRegRead(AR531X_PROC1);
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u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
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u32 dma1 = sysRegRead(AR531X_DMA1);
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u32 dmaAddr = sysRegRead(AR531X_DMAADDR); /* clears error state */
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printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
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procAddr, proc1, dmaAddr, dma1);
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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static struct irqaction ar5312_ahb_proc_interrupt = {
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.handler = ar5312_ahb_proc_handler,
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.flags = IRQF_DISABLED,
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.name = "ar5312_ahb_proc_interrupt",
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};
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static struct irqaction cascade = {
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.handler = no_action,
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.flags = IRQF_DISABLED,
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.name = "cascade",
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};
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void __init ar5312_misc_intr_init(int irq_base)
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{
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int i;
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for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &ar5312_misc_intr_controller;
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}
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setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
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setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
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}
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