180 lines
5.4 KiB
Diff
180 lines
5.4 KiB
Diff
From 5e1c00983efeca4522ac2e8574e3e3997d26a203 Mon Sep 17 00:00:00 2001
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From: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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Date: Fri, 29 Apr 2016 12:17:21 -0400
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Subject: [PATCH 074/102] mtd: mediatek: device tree docs for MTK Smart Device
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Gen1 NAND
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This patch adds documentation support for Smart Device Gen1 type of
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NAND controllers.
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Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
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---
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Documentation/devicetree/bindings/mtd/mtk-nand.txt | 161 ++++++++++++++++++++
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1 file changed, 161 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mtd/mtk-nand.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mtd/mtk-nand.txt
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@@ -0,0 +1,161 @@
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+MTK SoCs NAND FLASH controller (NFC) DT binding
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+
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+This file documents the device tree bindings for MTK SoCs NAND controllers.
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+The functional split of the controller requires two drivers to operate:
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+the nand controller interface driver and the ECC engine driver.
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+
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+The hardware description for both devices must be captured as device
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+tree nodes.
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+
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+1) NFC NAND Controller Interface (NFI):
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+=======================================
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+
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+The first part of NFC is NAND Controller Interface (NFI) HW.
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+Required NFI properties:
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+- compatible: Should be "mediatek,mtxxxx-nfc".
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+- reg: Base physical address and size of NFI.
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+- interrupts: Interrupts of NFI.
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+- clocks: NFI required clocks.
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+- clock-names: NFI clocks internal name.
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+- status: Disabled default. Then set "okay" by platform.
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+- ecc-engine: Required ECC Engine node.
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+- #address-cells: NAND chip index, should be 1.
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+- #size-cells: Should be 0.
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+
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+Example:
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+
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+ nandc: nfi@1100d000 {
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+ compatible = "mediatek,mt2701-nfc";
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+ reg = <0 0x1100d000 0 0x1000>;
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+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI>,
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+ <&pericfg CLK_PERI_NFI_PAD>;
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+ clock-names = "nfi_clk", "pad_clk";
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+ status = "disabled";
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+ ecc-engine = <&bch>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+Platform related properties, should be set in {platform_name}.dts:
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+- children nodes: NAND chips.
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+
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+Children nodes properties:
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+- reg: Chip Select Signal, default 0.
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+ Set as reg = <0>, <1> when need 2 CS.
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+Optional:
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+- nand-on-flash-bbt: Store BBT on NAND Flash.
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+- nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
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+- nand-ecc-step-size: Number of data bytes covered by a single ECC step.
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+ The controller only supports 512 and 1024.
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+ For large page NANDs ther recommended value is 1024.
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+- nand-ecc-strength: Number of bits to correct per ECC step.
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+ The valid values that the controller supports are: 4, 6,
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+ 8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
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+ 48, 52, 56, 60.
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+ The strength should be calculated as follows:
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+ E = (S - F) * 8 / 14
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+ S = O / (P / Q)
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+ E :nand-ecc-strength;
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+ S :spare size per sector;
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+ F : FDM size, should be in the range [1,8].
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+ It is used to store free oob data.
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+ O : oob size;
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+ P : page size;
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+ Q :nand-ecc-step-size
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+ If the result does not match any one of the listed
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+ choices above, please select the smaller valid value from
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+ the list.
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+ (otherwise the driver will do the clamping at runtime).
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+- vmch-supply: NAND power supply.
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+- pinctrl-names: Default NAND pin GPIO setting name.
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+- pinctrl-0: GPIO setting node.
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+
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+Example:
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+ &pio {
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+ nand_pins_default: nanddefault {
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+ pins_dat {
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+ pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
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+ <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
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+ <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
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+ <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
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+ <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
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+ <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
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+ <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
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+ <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
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+ <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
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+ input-enable;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-up;
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+ };
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+
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+ pins_we {
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+ pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+
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+ pins_ale {
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+ pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+ };
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+ };
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+
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+ &nandc {
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+ status = "okay";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&nand_pins_default>;
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+ nand@0 {
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+ reg = <0>;
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+ nand-on-flash-bbt;
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+ nand-ecc-mode = "hw";
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+ nand-ecc-strength = <24>;
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+ nand-ecc-step-size = <1024>;
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+ };
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+ };
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+
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+NAND chip optional subnodes:
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+- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
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+
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+Example:
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+ nand@0 {
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ preloader@0 {
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+ label = "pl";
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+ read-only;
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+ reg = <0x00000000 0x00400000>;
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+ };
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+ android@0x00400000 {
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+ label = "android";
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+ reg = <0x00400000 0x12c00000>;
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+ };
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+ };
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+ };
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+
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+2) ECC Engine:
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+==============
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+
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+Required BCH properties:
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+- compatible: Should be "mediatek,mtxxxx-ecc".
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+- reg: Base physical address and size of ECC.
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+- interrupts: Interrupts of ECC.
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+- clocks: ECC required clocks.
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+- clock-names: ECC clocks internal name.
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+- status: Disabled default. Then set "okay" by platform.
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+
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+Example:
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+
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+ bch: ecc@1100e000 {
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+ compatible = "mediatek,mt2701-ecc";
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+ reg = <0 0x1100e000 0 0x1000>;
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+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
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+ clock-names = "nfiecc_clk";
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+ status = "disabled";
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+ };
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