29 lines
1.1 KiB
Diff
29 lines
1.1 KiB
Diff
From ae28413b3b8901ea00af3571e1c90d0228976e16 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 4 Jan 2016 20:23:57 +0100
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Subject: [PATCH 80/81] MIPS: ralink: fix USB frequency scaling
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Commit 418d29c87061 ("MIPS: ralink: Unify SoC id handling") was not fully
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correct. The logic for the SoC check got inverted. We need to check if it
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is not a MT76x8.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/11992/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/ralink/mt7620.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -442,7 +442,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10000e00.uart2", periph_rate);
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ralink_clk_add("10180000.wmac", xtal_rate);
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- if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {
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+ if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be
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* too low for USB to function properly. Adjust the busses
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