0e2586a774
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 39220
335 lines
8.0 KiB
Diff
335 lines
8.0 KiB
Diff
--- a/drivers/spi/spi-rt2880.c
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+++ b/drivers/spi/spi-rt2880.c
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@@ -21,8 +21,11 @@
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#include <linux/io.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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+#include <linux/of_device.h>
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#include <linux/platform_device.h>
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+#include <ralink_regs.h>
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+
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#define DRIVER_NAME "spi-rt2880"
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/* only one slave is supported*/
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#define RALINK_NUM_CHIPSELECTS 1
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@@ -63,6 +66,25 @@
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/* SPIFIFOSTAT register bit field */
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#define SPIFIFOSTAT_TXFULL BIT(17)
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+#define MT7621_SPI_TRANS 0x00
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+#define SPITRANS_BUSY BIT(16)
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+#define MT7621_SPI_OPCODE 0x04
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+#define MT7621_SPI_DATA0 0x08
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+#define SPI_CTL_TX_RX_CNT_MASK 0xff
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+#define SPI_CTL_START BIT(8)
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+#define MT7621_SPI_POLAR 0x38
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+#define MT7621_SPI_MASTER 0x28
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+#define MT7621_SPI_SPACE 0x3c
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+
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+struct rt2880_spi;
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+
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+struct rt2880_spi_ops {
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+ void (*init_hw)(struct rt2880_spi *rs);
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+ void (*set_cs)(struct rt2880_spi *rs, int enable);
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+ int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
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+ unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
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+};
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+
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struct rt2880_spi {
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struct spi_master *master;
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void __iomem *base;
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@@ -70,6 +92,8 @@ struct rt2880_spi {
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unsigned int speed;
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struct clk *clk;
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spinlock_t lock;
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+
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+ struct rt2880_spi_ops *ops;
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};
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static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
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@@ -149,6 +173,17 @@ static int rt2880_spi_baudrate_set(struc
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return 0;
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}
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+static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
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+{
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+/* u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
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+
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+ // set default clock to hclk/5
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+ master &= ~(0xfff << 16);
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+ master |= 0x3 << 16;
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+*/
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+ return 0;
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+}
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+
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/*
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* called only when no transfer is active on the bus
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*/
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@@ -164,7 +199,7 @@ rt2880_spi_setup_transfer(struct spi_dev
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if (rs->speed != speed) {
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dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
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- rc = rt2880_spi_baudrate_set(spi, speed);
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+ rc = rs->ops->baudrate_set(spi, speed);
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if (rc)
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return rc;
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}
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@@ -180,6 +215,17 @@ static void rt2880_spi_set_cs(struct rt2
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rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
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}
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+static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
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+{
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+ u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
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+
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+ if (enable)
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+ polar |= 1;
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+ else
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+ polar &= ~1;
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+ rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
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+}
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+
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static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
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{
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int i;
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@@ -198,8 +244,26 @@ static inline int rt2880_spi_wait_till_r
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return -ETIMEDOUT;
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}
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+static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
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+{
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+ int i;
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+
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+ for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
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+ u32 status;
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+
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+ status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
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+ if ((status & SPITRANS_BUSY) == 0) {
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+ return 0;
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+ }
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+ cpu_relax();
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+ udelay(1);
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+ }
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+
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+ return -ETIMEDOUT;
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+}
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+
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static unsigned int
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-rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
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+rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
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{
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struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
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unsigned count = 0;
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@@ -239,6 +303,100 @@ out:
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return count;
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}
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+static unsigned int
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+mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
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+{
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+ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
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+ struct spi_transfer *next = NULL;
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+ const u8 *tx = xfer->tx_buf;
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+ u8 *rx = NULL;
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+ u32 trans;
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+ int len = xfer->len;
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+
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+ if (!tx)
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+ return 0;
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+
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+ if (!list_is_last(&xfer->transfer_list, list)) {
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+ next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
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+ rx = next->rx_buf;
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+ }
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+
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+ trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
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+ trans &= ~SPI_CTL_TX_RX_CNT_MASK;
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+
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+ if (tx) {
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+ u32 data0 = 0, opcode = 0;
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+
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+ switch (xfer->len) {
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+ case 8:
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+ data0 |= tx[7] << 24;
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+ case 7:
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+ data0 |= tx[6] << 16;
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+ case 6:
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+ data0 |= tx[5] << 8;
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+ case 5:
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+ data0 |= tx[4];
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+ case 4:
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+ opcode |= tx[3] << 8;
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+ case 3:
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+ opcode |= tx[2] << 16;
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+ case 2:
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+ opcode |= tx[1] << 24;
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+ case 1:
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+ opcode |= tx[0];
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+ break;
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+
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+ default:
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+ dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
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+ return -EINVAL;
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+ }
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+
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+ rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
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+ rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
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+ trans |= xfer->len;
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+ }
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+
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+ if (rx)
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+ trans |= (next->len << 4);
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+ rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
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+ trans |= SPI_CTL_START;
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+ rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
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+
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+ mt7621_spi_wait_till_ready(rs);
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+
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+ if (rx) {
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+ u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
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+ u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
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+
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+ switch (next->len) {
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+ case 8:
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+ rx[7] = (opcode >> 24) & 0xff;
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+ case 7:
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+ rx[6] = (opcode >> 16) & 0xff;
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+ case 6:
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+ rx[5] = (opcode >> 8) & 0xff;
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+ case 5:
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+ rx[4] = opcode & 0xff;
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+ case 4:
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+ rx[3] = (data0 >> 24) & 0xff;
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+ case 3:
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+ rx[2] = (data0 >> 16) & 0xff;
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+ case 2:
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+ rx[1] = (data0 >> 8) & 0xff;
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+ case 1:
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+ rx[0] = data0 & 0xff;
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+ break;
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+
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+ default:
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+ dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
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+ return -EINVAL;
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+ }
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+ len += next->len;
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+ }
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+
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+ return len;
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+}
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+
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static int rt2880_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *m)
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{
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@@ -280,25 +438,25 @@ static int rt2880_spi_transfer_one_messa
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}
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if (!cs_active) {
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- rt2880_spi_set_cs(rs, 1);
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+ rs->ops->set_cs(rs, 1);
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cs_active = 1;
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}
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if (t->len)
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- m->actual_length += rt2880_spi_write_read(spi, t);
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+ m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (t->cs_change) {
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- rt2880_spi_set_cs(rs, 0);
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+ rs->ops->set_cs(rs, 0);
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cs_active = 0;
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}
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}
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msg_done:
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if (cs_active)
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- rt2880_spi_set_cs(rs, 0);
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+ rs->ops->set_cs(rs, 0);
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m->status = status;
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spi_finalize_current_message(master);
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@@ -334,8 +492,41 @@ static void rt2880_spi_reset(struct rt28
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rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
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}
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+static void mt7621_spi_reset(struct rt2880_spi *rs)
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+{
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+ u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
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+
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+ master &= ~(0xfff << 16);
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+ master |= 3 << 16;
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+
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+ master |= 7 << 29;
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+ rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
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+}
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+
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+static struct rt2880_spi_ops spi_ops[] = {
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+ {
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+ .init_hw = rt2880_spi_reset,
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+ .set_cs = rt2880_spi_set_cs,
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+ .baudrate_set = rt2880_spi_baudrate_set,
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+ .write_read = rt2880_spi_write_read,
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+ }, {
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+ .init_hw = mt7621_spi_reset,
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+ .set_cs = mt7621_spi_set_cs,
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+ .baudrate_set = mt7621_spi_baudrate_set,
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+ .write_read = mt7621_spi_write_read,
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+ },
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+};
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+
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+static const struct of_device_id rt2880_spi_match[] = {
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+ { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
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+ { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, rt2880_spi_match);
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+
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static int rt2880_spi_probe(struct platform_device *pdev)
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{
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+ const struct of_device_id *match;
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struct spi_master *master;
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struct rt2880_spi *rs;
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unsigned long flags;
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@@ -344,6 +535,10 @@ static int rt2880_spi_probe(struct platf
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int status = 0;
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struct clk *clk;
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+ match = of_match_device(rt2880_spi_match, &pdev->dev);
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+ if (!match)
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+ return -EINVAL;
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+
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(base))
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@@ -382,12 +577,13 @@ static int rt2880_spi_probe(struct platf
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rs->clk = clk;
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rs->master = master;
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rs->sys_freq = clk_get_rate(rs->clk);
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+ rs->ops = (struct rt2880_spi_ops *) match->data;
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dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
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spin_lock_irqsave(&rs->lock, flags);
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device_reset(&pdev->dev);
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- rt2880_spi_reset(rs);
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+ rs->ops->init_hw(rs);
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return spi_register_master(master);
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}
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@@ -408,12 +604,6 @@ static int rt2880_spi_remove(struct plat
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MODULE_ALIAS("platform:" DRIVER_NAME);
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-static const struct of_device_id rt2880_spi_match[] = {
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- { .compatible = "ralink,rt2880-spi" },
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- {},
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-};
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-MODULE_DEVICE_TABLE(of, rt2880_spi_match);
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-
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static struct platform_driver rt2880_spi_driver = {
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.driver = {
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.name = DRIVER_NAME,
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