40 lines
1.2 KiB
Diff
40 lines
1.2 KiB
Diff
From 3f6b346e1dd83c4f43d94aefa0520ffdfafd5f0b Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <blogic@openwrt.org>
|
|
Date: Mon, 20 May 2013 20:30:11 +0200
|
|
Subject: [PATCH 05/33] MIPS: ralink: make mt7620 ram detect verbose
|
|
|
|
Make the code print which of SDRAM, DDR1 or DDR2 was detected.
|
|
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
|
---
|
|
arch/mips/ralink/mt7620.c | 3 +++
|
|
1 file changed, 3 insertions(+)
|
|
|
|
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
|
|
index 0018b1a..ccdec5a 100644
|
|
--- a/arch/mips/ralink/mt7620.c
|
|
+++ b/arch/mips/ralink/mt7620.c
|
|
@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
|
|
|
|
switch (dram_type) {
|
|
case SYSCFG0_DRAM_TYPE_SDRAM:
|
|
+ pr_info("Board has SDRAM\n");
|
|
soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
|
|
soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
|
|
break;
|
|
|
|
case SYSCFG0_DRAM_TYPE_DDR1:
|
|
+ pr_info("Board has DDR1\n");
|
|
soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
|
|
soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
|
|
break;
|
|
|
|
case SYSCFG0_DRAM_TYPE_DDR2:
|
|
+ pr_info("Board has DDR2\n");
|
|
soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
|
|
soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
|
|
break;
|
|
--
|
|
1.7.10.4
|
|
|