346 lines
10 KiB
Diff
346 lines
10 KiB
Diff
From 0f85e79f6f01f50cb703866a555085a9c65bad2f Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 29 Sep 2011 20:31:54 +0200
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Subject: [PATCH 21/24] MIPS: lantiq: adds cache split
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---
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arch/mips/Kconfig | 22 ++++++
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arch/mips/kernel/vpe.c | 66 ++++++++++++++++++
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arch/mips/mm/c-r4k.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 260 insertions(+), 0 deletions(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -1922,6 +1922,28 @@ config IFX_VPE_EXT
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help
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IFX included extensions in APRP
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+config IFX_VPE_CACHE_SPLIT
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+ bool "IFX Cache Split Ways"
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+ depends on IFX_VPE_EXT
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+ help
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+ IFX extension for reserving (splitting) cache ways among VPEs. You must
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+ give kernel command line arguments vpe_icache_shared=0 or
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+ vpe_dcache_shared=0 to enable splitting of icache or dcache
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+ respectively. Then you can specify which cache ways should be
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+ assigned to which VPE. There are total 8 cache ways, 4 each
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+ for dcache and icache: dcache_way0, dcache_way1,dcache_way2,
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+ dcache_way3 and icache_way0,icache_way1, icache_way2,icache_way3.
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+
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+ For example, if you specify vpe_icache_shared=0 and icache_way2=1,
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+ then the 3rd icache way will be assigned to VPE0 and denied in VPE1.
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+
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+ For icache, software is required to make at least one cache way available
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+ for a VPE at all times i.e., one can't assign all the icache ways to one
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+ VPE.
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+
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+ By default, vpe_dcache_shared and vpe_icache_shared are set to 1
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+ (i.e., both icache and dcache are shared among VPEs)
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+
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config PERFCTRS
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bool "34K Performance counters"
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depends on MIPS_MT && PROC_FS
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--- a/arch/mips/kernel/vpe.c
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+++ b/arch/mips/kernel/vpe.c
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@@ -128,6 +128,13 @@ __setup("vpe1_wdog_timeout=", wdog_timeo
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EXPORT_SYMBOL(vpe1_wdog_timeout);
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#endif
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+
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+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT /* Code for splitting the cache ways among VPEs. */
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+extern int vpe_icache_shared,vpe_dcache_shared;
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+extern int icache_way0,icache_way1,icache_way2,icache_way3;
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+extern int dcache_way0,dcache_way1,dcache_way2,dcache_way3;
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+#endif
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+
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/* grab the likely amount of memory we will need. */
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#ifdef CONFIG_MIPS_VPE_LOADER_TOM
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#define P_SIZE (2 * 1024 * 1024)
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@@ -866,6 +873,65 @@ static int vpe_run(struct vpe * v)
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/* enable this VPE */
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write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
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+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT
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+ if ( (!vpe_icache_shared) || (!vpe_dcache_shared) ) {
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+
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+ /* PCP bit must be 1 to split the cache */
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+ if(read_c0_mvpconf0() & MVPCONF0_PCP) {
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+
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+ if ( !vpe_icache_shared ){
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+ write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0()) & ~VPECONF0_ICS);
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+
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+ /*
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+ * If any cache way is 1, then that way is denied
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+ * in VPE1. Otherwise assign that way to VPE1.
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+ */
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+ if (!icache_way0)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX0 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX0 );
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+ if (!icache_way1)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX1 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX1 );
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+ if (!icache_way2)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX2 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX2 );
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+ if (!icache_way3)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX3 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX3 );
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+ }
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+
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+ if ( !vpe_dcache_shared ) {
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+ write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0()) & ~VPECONF0_DCS);
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+
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+ /*
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+ * If any cache way is 1, then that way is denied
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+ * in VPE1. Otherwise assign that way to VPE1.
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+ */
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+ if (!dcache_way0)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX0 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX0 );
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+ if (!dcache_way1)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX1 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX1 );
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+ if (!dcache_way2)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX2 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX2 );
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+ if (!dcache_way3)
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX3 );
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+ else
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+ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX3 );
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+ }
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+ }
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+ }
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+#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */
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+
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/* clear out any left overs from a previous program */
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write_vpe_c0_status(0);
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write_vpe_c0_cause(0);
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -1350,6 +1350,106 @@ static int __init setcoherentio(char *st
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__setup("coherentio", setcoherentio);
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#endif
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+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT /* Code for splitting the cache ways among VPEs. */
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+
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+#include <asm/mipsmtregs.h>
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+
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+/*
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+ * By default, vpe_icache_shared and vpe_dcache_shared
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+ * values are 1 i.e., both icache and dcache are shared
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+ * among the VPEs.
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+ */
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+
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+int vpe_icache_shared = 1;
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+static int __init vpe_icache_shared_val(char *str)
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+{
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+ get_option(&str, &vpe_icache_shared);
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+ return 1;
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+}
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+__setup("vpe_icache_shared=", vpe_icache_shared_val);
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+EXPORT_SYMBOL(vpe_icache_shared);
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+
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+int vpe_dcache_shared = 1;
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+static int __init vpe_dcache_shared_val(char *str)
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+{
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+ get_option(&str, &vpe_dcache_shared);
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+ return 1;
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+}
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+__setup("vpe_dcache_shared=", vpe_dcache_shared_val);
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+EXPORT_SYMBOL(vpe_dcache_shared);
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+
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+/*
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+ * Software is required to make atleast one icache
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+ * way available for a VPE at all times i.e., one
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+ * can't assign all the icache ways to one VPE.
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+ */
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+
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+int icache_way0 = 0;
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+static int __init icache_way0_val(char *str)
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+{
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+ get_option(&str, &icache_way0);
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+ return 1;
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+}
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+__setup("icache_way0=", icache_way0_val);
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+
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+int icache_way1 = 0;
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+static int __init icache_way1_val(char *str)
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+{
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+ get_option(&str, &icache_way1);
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+ return 1;
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+}
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+__setup("icache_way1=", icache_way1_val);
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+
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+int icache_way2 = 0;
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+static int __init icache_way2_val(char *str)
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+{
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+ get_option(&str, &icache_way2);
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+ return 1;
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+}
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+__setup("icache_way2=", icache_way2_val);
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+
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+int icache_way3 = 0;
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+static int __init icache_way3_val(char *str)
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+{
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+ get_option(&str, &icache_way3);
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+ return 1;
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+}
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+__setup("icache_way3=", icache_way3_val);
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+
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+int dcache_way0 = 0;
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+static int __init dcache_way0_val(char *str)
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+{
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+ get_option(&str, &dcache_way0);
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+ return 1;
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+}
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+__setup("dcache_way0=", dcache_way0_val);
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+
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+int dcache_way1 = 0;
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+static int __init dcache_way1_val(char *str)
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+{
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+ get_option(&str, &dcache_way1);
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+ return 1;
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+}
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+__setup("dcache_way1=", dcache_way1_val);
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+
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+int dcache_way2 = 0;
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+static int __init dcache_way2_val(char *str)
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+{
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+ get_option(&str, &dcache_way2);
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+ return 1;
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+}
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+__setup("dcache_way2=", dcache_way2_val);
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+
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+int dcache_way3 = 0;
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+static int __init dcache_way3_val(char *str)
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+{
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+ get_option(&str, &dcache_way3);
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+ return 1;
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+}
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+__setup("dcache_way3=", dcache_way3_val);
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+
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+#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */
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+
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void __cpuinit r4k_cache_init(void)
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{
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extern void build_clear_page(void);
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@@ -1369,6 +1469,78 @@ void __cpuinit r4k_cache_init(void)
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break;
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}
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+#ifdef CONFIG_IFX_VPE_CACHE_SPLIT
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+ /*
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+ * We split the cache ways appropriately among the VPEs
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+ * based on cache ways values we received as command line
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+ * arguments
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+ */
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+ if ( (!vpe_icache_shared) || (!vpe_dcache_shared) ){
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+
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+ /* PCP bit must be 1 to split the cache */
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+ if(read_c0_mvpconf0() & MVPCONF0_PCP) {
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+
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+ /* Set CPA bit which enables us to modify VPEOpt register */
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+ write_c0_mvpcontrol((read_c0_mvpcontrol()) | MVPCONTROL_CPA);
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+
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+ if ( !vpe_icache_shared ){
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+ write_c0_vpeconf0((read_c0_vpeconf0()) & ~VPECONF0_ICS);
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+ /*
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+ * If any cache way is 1, then that way is denied
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+ * in VPE0. Otherwise assign that way to VPE0.
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+ */
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+ printk(KERN_DEBUG "icache is split\n");
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+ printk(KERN_DEBUG "icache_way0=%d icache_way1=%d icache_way2=%d icache_way3=%d\n",
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+ icache_way0, icache_way1,icache_way2, icache_way3);
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+ if (icache_way0)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX0 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX0 );
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+ if (icache_way1)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX1 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX1 );
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+ if (icache_way2)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX2 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX2 );
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+ if (icache_way3)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX3 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX3 );
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+ }
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+
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+ if ( !vpe_dcache_shared ) {
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+ /*
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+ * If any cache way is 1, then that way is denied
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+ * in VPE0. Otherwise assign that way to VPE0.
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+ */
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+ printk(KERN_DEBUG "dcache is split\n");
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+ printk(KERN_DEBUG "dcache_way0=%d dcache_way1=%d dcache_way2=%d dcache_way3=%d\n",
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+ dcache_way0, dcache_way1, dcache_way2, dcache_way3);
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+ write_c0_vpeconf0((read_c0_vpeconf0()) & ~VPECONF0_DCS);
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+ if (dcache_way0)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX0 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX0 );
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+ if (dcache_way1)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX1 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX1 );
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+ if (dcache_way2)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX2 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX2 );
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+ if (dcache_way3)
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+ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX3 );
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+ else
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+ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX3 );
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+ }
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+ }
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+ }
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+
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+#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */
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+
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probe_pcache();
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setup_scache();
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--- a/arch/mips/lantiq/setup.c
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+++ b/arch/mips/lantiq/setup.c
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@@ -18,10 +18,11 @@
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#include "devices.h"
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#include "prom.h"
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+/* assume 16M as default incase uboot fails to pass proper ramsize */
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+unsigned long physical_memsize = 16L;
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+
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void __init plat_mem_setup(void)
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{
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- /* assume 16M as default incase uboot fails to pass proper ramsize */
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- unsigned long memsize = 16;
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char **envp = (char **) KSEG1ADDR(fw_arg2);
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ioport_resource.start = IOPORT_RESOURCE_START;
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@@ -35,13 +36,13 @@ void __init plat_mem_setup(void)
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char *e = (char *)KSEG1ADDR(*envp);
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if (!strncmp(e, "memsize=", 8)) {
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e += 8;
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- if (strict_strtoul(e, 0, &memsize))
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+ if (strict_strtoul(e, 0, &physical_memsize))
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pr_warn("bad memsize specified\n");
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}
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envp++;
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}
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- memsize *= 1024 * 1024;
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- add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
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+ physical_memsize *= 1024 * 1024;
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+ add_memory_region(0x00000000, physical_memsize, BOOT_MEM_RAM);
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}
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static int __init
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