112 lines
3.8 KiB
Diff
112 lines
3.8 KiB
Diff
From c225f78660cd61914f25dd00499c7ae71d1d6919 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime.ripard@free-electrons.com>
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Date: Wed, 5 Feb 2014 14:05:03 +0100
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Subject: [PATCH] clk: sunxi: Add support for PLL6 on the A31
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The A31 has a slightly different PLL6 clock. Add support for this new clock in
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our driver.
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
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drivers/clk/sunxi/clk-sunxi.c | 45 +++++++++++++++++++++++
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2 files changed, 46 insertions(+)
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diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
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index ca2b692..c37c764 100644
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -11,6 +11,7 @@ Required properties:
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"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
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"allwinner,sun4i-pll5-clk" - for the PLL5 clock
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"allwinner,sun4i-pll6-clk" - for the PLL6 clock
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+ "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
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"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
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"allwinner,sun4i-axi-clk" - for the AXI clock
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"allwinner,sun4i-axi-gates-clk" - for the AXI gates
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index a779c31..d4cf297 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -252,7 +252,38 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
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*n = DIV_ROUND_UP(div, (*k+1));
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}
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+/**
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+ * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6
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+ * PLL6 rate is calculated as follows
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+ * rate = parent_rate * n * (k + 1) / 2
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+ * parent_rate is always 24Mhz
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+ */
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+
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+static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div;
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+
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+ /*
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+ * We always have 24MHz / 2, so we can just say that our
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+ * parent clock is 12MHz.
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+ */
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+ parent_rate = parent_rate / 2;
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+
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+ /* Normalize value to a parent_rate multiple (24M / 2) */
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+ div = *freq / parent_rate;
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+ *freq = parent_rate * div;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ *k = div / 32;
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+ if (*k > 3)
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+ *k = 3;
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+ *n = DIV_ROUND_UP(div, (*k+1));
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+}
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/**
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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@@ -420,6 +451,13 @@ static struct clk_factors_config sun4i_pll5_config = {
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.kwidth = 2,
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};
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+static struct clk_factors_config sun6i_a31_pll6_config = {
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+ .nshift = 8,
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+ .nwidth = 5,
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+ .kshift = 4,
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+ .kwidth = 2,
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+};
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+
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static struct clk_factors_config sun4i_apb1_config = {
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.mshift = 0,
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.mwidth = 5,
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@@ -469,6 +507,12 @@ static const struct factors_data sun4i_pll6_data __initconst = {
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.name = "pll6",
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};
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+static const struct factors_data sun6i_a31_pll6_data __initconst = {
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+ .enable = 31,
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+ .table = &sun6i_a31_pll6_config,
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+ .getter = sun6i_a31_get_pll6_factors,
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+};
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+
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static const struct factors_data sun4i_apb1_data __initconst = {
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.table = &sun4i_apb1_config,
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.getter = sun4i_get_apb1_factors,
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@@ -1069,6 +1113,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
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static const struct of_device_id clk_factors_match[] __initconst = {
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{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
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{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
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+ {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_data,},
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{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
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{.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
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{.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
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--
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2.0.3
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