857 lines
29 KiB
C
857 lines
29 KiB
C
/*
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* SiliconBackplane Chipcommon core hardware definitions.
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*
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* The chipcommon core provides chip identification, SB control,
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* jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
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* gpio interface, extbus, and support for serial and parallel flashes.
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#ifndef _SBCHIPC_H
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#define _SBCHIPC_H
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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typedef volatile struct {
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uint32 chipid; /* 0x0 */
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uint32 capabilities;
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uint32 corecontrol; /* corerev >= 1 */
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uint32 bist;
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/* OTP */
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uint32 otpstatus; /* 0x10, corerev >= 10 */
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uint32 otpcontrol;
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uint32 otpprog;
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uint32 PAD;
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/* Interrupt control */
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uint32 intstatus; /* 0x20 */
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uint32 intmask;
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uint32 chipcontrol; /* 0x28, rev >= 11 */
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uint32 chipstatus; /* 0x2c, rev >= 11 */
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/* Jtag Master */
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uint32 jtagcmd; /* 0x30, rev >= 10 */
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uint32 jtagir;
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uint32 jtagdr;
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uint32 jtagctrl;
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/* serial flash interface registers */
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uint32 flashcontrol; /* 0x40 */
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uint32 flashaddress;
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uint32 flashdata;
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uint32 PAD[1];
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/* Silicon backplane configuration broadcast control */
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uint32 broadcastaddress; /* 0x50 */
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uint32 broadcastdata;
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/* gpio - cleared only by power-on-reset */
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uint32 gpiopullup; /* 0x58, corerev >= 20 */
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uint32 gpiopulldown; /* 0x5c, corerev >= 20 */
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uint32 gpioin; /* 0x60 */
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uint32 gpioout;
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uint32 gpioouten;
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uint32 gpiocontrol;
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uint32 gpiointpolarity;
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uint32 gpiointmask;
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/* GPIO events corerev >= 11 */
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uint32 gpioevent;
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uint32 gpioeventintmask;
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/* Watchdog timer */
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uint32 watchdog; /* 0x80 */
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/* GPIO events corerev >= 11 */
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uint32 gpioeventintpolarity;
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/* GPIO based LED powersave registers corerev >= 16 */
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uint32 gpiotimerval; /* 0x88 */
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uint32 gpiotimeroutmask;
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/* clock control */
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uint32 clockcontrol_n; /* 0x90 */
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uint32 clockcontrol_sb; /* aka m0 */
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uint32 clockcontrol_pci; /* aka m1 */
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uint32 clockcontrol_m2; /* mii/uart/mipsref */
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uint32 clockcontrol_m3; /* cpu */
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uint32 clkdiv; /* corerev >= 3 */
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uint32 PAD[2];
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/* pll delay registers (corerev >= 4) */
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uint32 pll_on_delay; /* 0xb0 */
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uint32 fref_sel_delay;
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uint32 slow_clk_ctl; /* 5 < corerev < 10 */
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uint32 PAD[1];
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/* Instaclock registers (corerev >= 10) */
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uint32 system_clk_ctl; /* 0xc0 */
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uint32 clkstatestretch;
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uint32 PAD[14];
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/* ExtBus control registers (corerev >= 3) */
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uint32 pcmcia_config; /* 0x100 */
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uint32 pcmcia_memwait;
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uint32 pcmcia_attrwait;
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uint32 pcmcia_iowait;
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uint32 ide_config;
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uint32 ide_memwait;
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uint32 ide_attrwait;
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uint32 ide_iowait;
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uint32 prog_config;
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uint32 prog_waitcount;
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uint32 flash_config;
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uint32 flash_waitcount;
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uint32 PAD[4];
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/* Enhanced Coexistance Interface (ECI) registers (corerev >= 21) */
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uint32 eci_output; /* 0x140 */
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uint32 eci_control;
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uint32 eci_inputlo;
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uint32 eci_inputmi;
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uint32 eci_inputhi;
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uint32 eci_inputintpolaritylo;
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uint32 eci_inputintpolaritymi;
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uint32 eci_inputintpolarityhi;
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uint32 eci_intmasklo;
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uint32 eci_intmaskmi;
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uint32 eci_intmaskhi;
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uint32 eci_eventlo;
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uint32 eci_eventmi;
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uint32 eci_eventhi;
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uint32 eci_eventmasklo;
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uint32 eci_eventmaskmi;
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uint32 eci_eventmaskhi;
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uint32 PAD[23];
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/* Clock control and hardware workarounds (corerev >= 20) */
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uint32 clk_ctl_st; /* 0x1e0 */
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uint32 hw_war;
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uint32 PAD[70];
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/* uarts */
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uint8 uart0data; /* 0x300 */
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uint8 uart0imr;
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uint8 uart0fcr;
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uint8 uart0lcr;
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uint8 uart0mcr;
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uint8 uart0lsr;
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uint8 uart0msr;
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uint8 uart0scratch;
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uint8 PAD[248]; /* corerev >= 1 */
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uint8 uart1data; /* 0x400 */
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uint8 uart1imr;
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uint8 uart1fcr;
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uint8 uart1lcr;
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uint8 uart1mcr;
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uint8 uart1lsr;
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uint8 uart1msr;
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uint8 uart1scratch;
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uint32 PAD[126];
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/* PMU registers (corerev >= 20) */
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uint32 pmucontrol; /* 0x600 */
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uint32 pmucapabilities;
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uint32 pmustatus;
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uint32 res_state;
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uint32 res_pending;
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uint32 pmutimer;
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uint32 min_res_mask;
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uint32 max_res_mask;
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uint32 res_table_sel;
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uint32 res_dep_mask;
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uint32 res_updn_timer;
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uint32 res_timer;
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uint32 clkstretch;
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uint32 pmuwatchdog;
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uint32 PAD[2];
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uint32 res_req_timer_sel;
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uint32 res_req_timer;
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uint32 res_req_mask;
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uint32 PAD;
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uint32 chipcontrol_addr;
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uint32 chipcontrol_data;
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uint32 regcontrol_addr;
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uint32 regcontrol_data;
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uint32 pllcontrol_addr;
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uint32 pllcontrol_data;
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uint32 PAD[102];
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uint16 otp[512];
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} chipcregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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/* corecontrol */
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#define CC_UE (1 << 0) /* uart enable */
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#define CC_CHIPID 0
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#define CC_CAPABILITIES 4
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#define CC_OTPST 0x10
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#define CC_CHIPST 0x2c
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#define CC_JTAGCMD 0x30
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#define CC_JTAGIR 0x34
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#define CC_JTAGDR 0x38
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#define CC_JTAGCTRL 0x3c
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#define CC_WATCHDOG 0x80
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#define CC_CLKC_N 0x90
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#define CC_CLKC_M0 0x94
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#define CC_CLKC_M1 0x98
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#define CC_CLKC_M2 0x9c
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#define CC_CLKC_M3 0xa0
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#define CC_CLKDIV 0xa4
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#define CC_SYS_CLK_CTL 0xc0
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#define CC_CLK_CTL_ST SB_CLK_CTL_ST
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#define PMU_CTL 0x600
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#define PMU_CAP 0x604
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#define PMU_ST 0x608
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#define PMU_TIMER 0x614
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#define PMU_MIN_RES_MASK 0x618
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#define PMU_MAX_RES_MASK 0x61c
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#define PMU_REG_CONTROL_ADDR 0x658
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#define PMU_REG_CONTROL_DATA 0x65C
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#define PMU_PLL_CONTROL_ADDR 0x660
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#define PMU_PLL_CONTROL_DATA 0x664
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#define CC_OTP 0x800 /* OTP address space */
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/* chipid */
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#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
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#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
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#define CID_REV_SHIFT 16 /* Chip Revision shift */
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#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
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#define CID_PKG_SHIFT 20 /* Package Option shift */
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#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
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#define CID_CC_SHIFT 24
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/* capabilities */
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#define CC_CAP_UARTS_MASK 0x00000003 /* Number of uarts */
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#define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
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#define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
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#define CC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
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#define CC_CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
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#define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
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#define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
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#define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
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#define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
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#define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
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#define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
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#define CC_CAP_PWR_CTL 0x00040000 /* Power control */
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#define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
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#define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
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#define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */
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#define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
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#define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
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#define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
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#define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
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#define CC_CAP_ECI 0x20000000 /* ECI Present, rev >= 21 */
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/* PLL type */
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#define PLL_NONE 0x00000000
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#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
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#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
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#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
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#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
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#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
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#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
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#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
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/* ALP clock on pre-PMU chips */
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#define ALP_CLOCK 20000000
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/* HT clock */
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#define HT_CLOCK 80000000
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/* watchdog clock */
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#define WATCHDOG_CLOCK_5354 32000 /* Hz */
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/* corecontrol */
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#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
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#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
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#define CC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */
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/* chipcontrol */
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#define CHIPCTRL_4321A0_DEFAULT 0x3a4
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#define CHIPCTRL_4321A1_DEFAULT 0x0a4
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/* Fields in the otpstatus register in rev >= 21 */
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#define OTPS_OL_MASK 0x000000ff
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#define OTPS_OL_MFG 0x00000001 /* manuf row is locked */
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#define OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */
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#define OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */
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#define OTPS_OL_GU 0x00000008 /* general use region is locked */
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#define OTPS_GUP_MASK 0x00000f00
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#define OTPS_GUP_SHIFT 8
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#define OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */
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#define OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */
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#define OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */
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#define OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */
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#define OTPS_READY 0x00001000
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#define OTPS_RV(x) (1 << (16 + (x)))
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/* Fields in the otpcontrol register in rev >= 21 */
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#define OTPC_PROGSEL 0x00000001
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#define OTPC_PCOUNT_MASK 0x0000000e
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#define OTPC_PCOUNT_SHIFT 1
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#define OTPC_VSEL_MASK 0x000000f0
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#define OTPC_VSEL_SHIFT 4
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#define OTPC_TMM_MASK 0x00000700
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#define OTPC_TMM_SHIFT 8
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#define OTPC_ODM 0x00000800
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#define OTPC_PROGEN 0x80000000
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/* Fields in otpprog in rev >= 21 */
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#define OTPP_COL_MASK 0x000000ff
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#define OTPP_COL_SHIFT 0
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#define OTPP_ROW_MASK 0x0000ff00
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#define OTPP_ROW_SHIFT 8
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#define OTPP_OC_MASK 0x0f000000
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#define OTPP_OC_SHIFT 24
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#define OTPP_READERR 0x10000000
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#define OTPP_VALUE_MASK 0x20000000
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#define OTPP_VALUE_SHIFT 29
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#define OTPP_START_BUSY 0x80000000
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/* Opcodes for OTPP_OC field */
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#define OTPPOC_READ 0
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#define OTPPOC_BIT_PROG 1
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#define OTPPOC_VERIFY 3
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#define OTPPOC_INIT 4
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#define OTPPOC_SET 5
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#define OTPPOC_RESET 6
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#define OTPPOC_OCST 7
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#define OTPPOC_ROW_LOCK 8
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#define OTPPOC_PRESCN_TEST 9
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/* jtagcmd */
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#define JCMD_START 0x80000000
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#define JCMD_BUSY 0x80000000
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#define JCMD_PAUSE 0x40000000
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#define JCMD0_ACC_MASK 0x0000f000
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#define JCMD0_ACC_IRDR 0x00000000
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#define JCMD0_ACC_DR 0x00001000
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#define JCMD0_ACC_IR 0x00002000
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#define JCMD0_ACC_RESET 0x00003000
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#define JCMD0_ACC_IRPDR 0x00004000
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#define JCMD0_ACC_PDR 0x00005000
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#define JCMD0_IRW_MASK 0x00000f00
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#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
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#define JCMD_ACC_IRDR 0x00000000
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#define JCMD_ACC_DR 0x00010000
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#define JCMD_ACC_IR 0x00020000
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#define JCMD_ACC_RESET 0x00030000
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#define JCMD_ACC_IRPDR 0x00040000
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#define JCMD_ACC_PDR 0x00050000
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#define JCMD_IRW_MASK 0x00001f00
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#define JCMD_IRW_SHIFT 8
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#define JCMD_DRW_MASK 0x0000003f
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/* jtagctrl */
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#define JCTRL_FORCE_CLK 4 /* Force clock */
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#define JCTRL_EXT_EN 2 /* Enable external targets */
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#define JCTRL_EN 1 /* Enable Jtag master */
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/* Fields in clkdiv */
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#define CLKD_SFLASH 0x0f000000
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#define CLKD_SFLASH_SHIFT 24
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#define CLKD_OTP 0x000f0000
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#define CLKD_OTP_SHIFT 16
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#define CLKD_JTAG 0x00000f00
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#define CLKD_JTAG_SHIFT 8
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#define CLKD_UART 0x000000ff
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/* intstatus/intmask */
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#define CI_GPIO 0x00000001 /* gpio intr */
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#define CI_EI 0x00000002 /* extif intr (corerev >= 3) */
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#define CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */
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#define CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */
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#define CI_ECI 0x00000010 /* eci intr (corerev >= 21) */
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#define CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */
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#define CI_UART 0x00000040 /* uart intr (corerev >= 21) */
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#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
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/* slow_clk_ctl */
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#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
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#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
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#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
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#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
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#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
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#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled,
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* 0: LPO is enabled
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*/
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#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,
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* 0: power logic control
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*/
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#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors
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* PLL clock disable requests from core
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*/
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#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't
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* disable crystal when appropriate
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*/
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#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
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#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
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#define SCC_CD_SHIFT 16
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/* system_clk_ctl */
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#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
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#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
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#define SYCC_FP 0x00000004 /* ForcePLLOn */
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#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
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#define SYCC_HR 0x00000010 /* Force HT */
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#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
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#define SYCC_CD_SHIFT 16
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/* pcmcia_iowait */
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#define PI_W0_MASK 0x0000003f /* waitcount0 */
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#define PI_W1_MASK 0x00001f00 /* waitcount1 */
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#define PI_W1_SHIFT 8
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#define PI_W2_MASK 0x001f0000 /* waitcount2 */
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#define PI_W2_SHIFT 16
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#define PI_W3_MASK 0x1f000000 /* waitcount3 */
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#define PI_W3_SHIFT 24
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/* prog_waitcount */
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#define PW_W0_MASK 0x0000001f /* waitcount0 */
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#define PW_W1_MASK 0x00001f00 /* waitcount1 */
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#define PW_W1_SHIFT 8
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#define PW_W2_MASK 0x001f0000 /* waitcount2 */
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#define PW_W2_SHIFT 16
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#define PW_W3_MASK 0x1f000000 /* waitcount3 */
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#define PW_W3_SHIFT 24
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#define PW_W0 0x0000000c
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#define PW_W1 0x00000a00
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#define PW_W2 0x00020000
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#define PW_W3 0x01000000
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/* watchdog */
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#define WATCHDOG_CLOCK 48000000 /* Hz */
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/* Fields in pmucontrol */
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#define PCTL_ILP_DIV_MASK 0xffff0000
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#define PCTL_ILP_DIV_SHIFT 16
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#define PCTL_NOILP_ON_WAIT 0x00000200
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#define PCTL_HT_REQ_EN 0x00000100
|
|
#define PCTL_ALP_REQ_EN 0x00000080
|
|
#define PCTL_XTALFREQ_MASK 0x0000007c
|
|
#define PCTL_XTALFREQ_SHIFT 2
|
|
#define PCTL_ILP_DIV_EN 0x00000002
|
|
#define PCTL_LPO_SEL 0x00000001
|
|
|
|
/* gpiotimerval */
|
|
#define GPIO_ONTIME_SHIFT 16
|
|
|
|
/* clockcontrol_n */
|
|
#define CN_N1_MASK 0x3f /* n1 control */
|
|
#define CN_N2_MASK 0x3f00 /* n2 control */
|
|
#define CN_N2_SHIFT 8
|
|
#define CN_PLLC_MASK 0xf0000 /* pll control */
|
|
#define CN_PLLC_SHIFT 16
|
|
|
|
/* clockcontrol_sb/pci/uart */
|
|
#define CC_M1_MASK 0x3f /* m1 control */
|
|
#define CC_M2_MASK 0x3f00 /* m2 control */
|
|
#define CC_M2_SHIFT 8
|
|
#define CC_M3_MASK 0x3f0000 /* m3 control */
|
|
#define CC_M3_SHIFT 16
|
|
#define CC_MC_MASK 0x1f000000 /* mux control */
|
|
#define CC_MC_SHIFT 24
|
|
|
|
/* N3M Clock control magic field values */
|
|
#define CC_F6_2 0x02 /* A factor of 2 in */
|
|
#define CC_F6_3 0x03 /* 6-bit fields like */
|
|
#define CC_F6_4 0x05 /* N1, M1 or M3 */
|
|
#define CC_F6_5 0x09
|
|
#define CC_F6_6 0x11
|
|
#define CC_F6_7 0x21
|
|
|
|
#define CC_F5_BIAS 5 /* 5-bit fields get this added */
|
|
|
|
#define CC_MC_BYPASS 0x08
|
|
#define CC_MC_M1 0x04
|
|
#define CC_MC_M1M2 0x02
|
|
#define CC_MC_M1M2M3 0x01
|
|
#define CC_MC_M1M3 0x11
|
|
|
|
/* Type 2 Clock control magic field values */
|
|
#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
|
|
#define CC_T2M2_BIAS 3 /* m2 bias */
|
|
|
|
#define CC_T2MC_M1BYP 1
|
|
#define CC_T2MC_M2BYP 2
|
|
#define CC_T2MC_M3BYP 4
|
|
|
|
/* Type 6 Clock control magic field values */
|
|
#define CC_T6_MMASK 1 /* bits of interest in m */
|
|
#define CC_T6_M0 120000000 /* sb clock for m = 0 */
|
|
#define CC_T6_M1 100000000 /* sb clock for m = 1 */
|
|
#define SB2MIPS_T6(sb) (2 * (sb))
|
|
|
|
/* Common clock base */
|
|
#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
|
|
#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
|
|
|
|
/* Clock control values for 200Mhz in 5350 */
|
|
#define CLKC_5350_N 0x0311
|
|
#define CLKC_5350_M 0x04020009
|
|
|
|
/* Flash types in the chipcommon capabilities register */
|
|
#define FLASH_NONE 0x000 /* No flash */
|
|
#define SFLASH_ST 0x100 /* ST serial flash */
|
|
#define SFLASH_AT 0x200 /* Atmel serial flash */
|
|
#define PFLASH 0x700 /* Parallel flash */
|
|
|
|
/* Bits in the ExtBus config registers */
|
|
#define CC_CFG_EN 0x0001 /* Enable */
|
|
#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
|
|
#define CC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */
|
|
#define CC_CFG_EM_SYNC 0x0002 /* Synchronous */
|
|
#define CC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */
|
|
#define CC_CFG_EM_IDE 0x0006 /* IDE */
|
|
#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
|
|
#define CC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */
|
|
#define CC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */
|
|
#define CC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */
|
|
#define CC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */
|
|
|
|
/* ExtBus address space */
|
|
#define CC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */
|
|
#define CC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */
|
|
#define CC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */
|
|
#define CC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */
|
|
#define CC_EB_IDE 0x1a800000 /* IDE memory base */
|
|
#define CC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */
|
|
#define CC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */
|
|
#define CC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */
|
|
#define CC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */
|
|
|
|
|
|
/* Start/busy bit in flashcontrol */
|
|
#define SFLASH_OPCODE 0x000000ff
|
|
#define SFLASH_ACTION 0x00000700
|
|
#define SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */
|
|
#define SFLASH_START 0x80000000
|
|
#define SFLASH_BUSY SFLASH_START
|
|
|
|
/* flashcontrol action codes */
|
|
#define SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */
|
|
#define SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */
|
|
#define SFLASH_ACT_OP3A 0x0200 /* opcode + 3 address bytes */
|
|
#define SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addres & 1 data bytes */
|
|
#define SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addres & 4 data bytes */
|
|
#define SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addres, 4 don't care & 4 data bytes */
|
|
#define SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addres, 1 don't care & 4 data bytes */
|
|
|
|
/* flashcontrol action+opcodes for ST flashes */
|
|
#define SFLASH_ST_WREN 0x0006 /* Write Enable */
|
|
#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
|
|
#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
|
|
#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
|
|
#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
|
|
#define SFLASH_ST_PP 0x0302 /* Page Program */
|
|
#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
|
|
#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
|
|
#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
|
|
#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
|
|
#define SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */
|
|
|
|
/* Status register bits for ST flashes */
|
|
#define SFLASH_ST_WIP 0x01 /* Write In Progress */
|
|
#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
|
|
#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
|
|
#define SFLASH_ST_BP_SHIFT 2
|
|
#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
|
|
|
|
/* flashcontrol action+opcodes for Atmel flashes */
|
|
#define SFLASH_AT_READ 0x07e8
|
|
#define SFLASH_AT_PAGE_READ 0x07d2
|
|
#define SFLASH_AT_BUF1_READ
|
|
#define SFLASH_AT_BUF2_READ
|
|
#define SFLASH_AT_STATUS 0x01d7
|
|
#define SFLASH_AT_BUF1_WRITE 0x0384
|
|
#define SFLASH_AT_BUF2_WRITE 0x0387
|
|
#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
|
|
#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
|
|
#define SFLASH_AT_BUF1_PROGRAM 0x0288
|
|
#define SFLASH_AT_BUF2_PROGRAM 0x0289
|
|
#define SFLASH_AT_PAGE_ERASE 0x0281
|
|
#define SFLASH_AT_BLOCK_ERASE 0x0250
|
|
#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
|
|
#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
|
|
#define SFLASH_AT_BUF1_LOAD 0x0253
|
|
#define SFLASH_AT_BUF2_LOAD 0x0255
|
|
#define SFLASH_AT_BUF1_COMPARE 0x0260
|
|
#define SFLASH_AT_BUF2_COMPARE 0x0261
|
|
#define SFLASH_AT_BUF1_REPROGRAM 0x0258
|
|
#define SFLASH_AT_BUF2_REPROGRAM 0x0259
|
|
|
|
/* Status register bits for Atmel flashes */
|
|
#define SFLASH_AT_READY 0x80
|
|
#define SFLASH_AT_MISMATCH 0x40
|
|
#define SFLASH_AT_ID_MASK 0x38
|
|
#define SFLASH_AT_ID_SHIFT 3
|
|
|
|
/*
|
|
* These are the UART port assignments, expressed as offsets from the base
|
|
* register. These assignments should hold for any serial port based on
|
|
* a 8250, 16450, or 16550(A).
|
|
*/
|
|
|
|
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
|
|
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
|
|
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
|
|
#define UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */
|
|
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
|
|
#define UART_IIR 2 /* In: Interrupt Identity Register */
|
|
#define UART_FCR 2 /* Out: FIFO Control Register */
|
|
#define UART_LCR 3 /* Out: Line Control Register */
|
|
#define UART_MCR 4 /* Out: Modem Control Register */
|
|
#define UART_LSR 5 /* In: Line Status Register */
|
|
#define UART_MSR 6 /* In: Modem Status Register */
|
|
#define UART_SCR 7 /* I/O: Scratch Register */
|
|
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
|
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
|
|
#define UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */
|
|
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
|
|
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
|
|
#define UART_LSR_RXRDY 0x01 /* Receiver ready */
|
|
#define UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */
|
|
|
|
/* Interrupt Identity Register (IIR) bits */
|
|
#define UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */
|
|
#define UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */
|
|
#define UART_IIR_MDM_CHG 0x0 /* Modem status changed */
|
|
#define UART_IIR_NOINT 0x1 /* No interrupt pending */
|
|
#define UART_IIR_THRE 0x2 /* THR empty */
|
|
#define UART_IIR_RCVD_DATA 0x4 /* Received data available */
|
|
#define UART_IIR_RCVR_STATUS 0x6 /* Receiver status */
|
|
#define UART_IIR_CHAR_TIME 0xc /* Character time */
|
|
|
|
/* Interrupt Enable Register (IER) bits */
|
|
#define UART_IER_EDSSI 8 /* enable modem status interrupt */
|
|
#define UART_IER_ELSI 4 /* enable receiver line status interrupt */
|
|
#define UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */
|
|
#define UART_IER_ERBFI 1 /* enable data available interrupt */
|
|
|
|
/* pmustatus */
|
|
#define PST_INTPEND 0x0040
|
|
#define PST_SBCLKST 0x0030
|
|
#define PST_ALPAVAIL 0x0008
|
|
#define PST_HTAVAIL 0x0004
|
|
#define PST_RESINIT 0x0003
|
|
|
|
/* pmucapabilities */
|
|
#define PCAP_REV_MASK 0x000000ff
|
|
|
|
/* PMU Resource Request Timer registers */
|
|
/* This is based on PmuRev0 */
|
|
#define PRRT_TIME_MASK 0x03ff
|
|
#define PRRT_INTEN 0x0400
|
|
#define PRRT_REQ_ACTIVE 0x0800
|
|
#define PRRT_ALP_REQ 0x1000
|
|
#define PRRT_HT_REQ 0x2000
|
|
|
|
/* PMU resource bit position */
|
|
#define PMURES_BIT(bit) (1 << (bit))
|
|
|
|
/* PMU corerev and chip specific PLL controls.
|
|
* PMU<rev>_PLL<num>_XXXX where <rev> is PMU corerev and <num> is an arbitary number
|
|
* to differentiate different PLLs controlled by the same PMU rev.
|
|
*/
|
|
/* pllcontrol registers */
|
|
/* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */
|
|
#define PMU0_PLL0_PLLCTL0 0
|
|
#define PMU0_PLL0_PC0_PDIV_MASK 1
|
|
#define PMU0_PLL0_PC0_PDIV_FREQ 25000
|
|
#define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038
|
|
#define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3
|
|
#define PMU0_PLL0_PC0_DIV_ARM_BASE 8
|
|
|
|
/* PC0_DIV_ARM for PLLOUT_ARM */
|
|
#define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0
|
|
#define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1
|
|
#define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2
|
|
#define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */
|
|
#define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4
|
|
#define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5
|
|
#define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6
|
|
#define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7
|
|
|
|
/* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */
|
|
#define PMU0_PLL0_PLLCTL1 1
|
|
#define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000
|
|
#define PMU0_PLL0_PC1_WILD_INT_SHIFT 28
|
|
#define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00
|
|
#define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8
|
|
#define PMU0_PLL0_PC1_STOP_MOD 0x00000040
|
|
|
|
/* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */
|
|
#define PMU0_PLL0_PLLCTL2 2
|
|
#define PMU0_PLL0_PC2_WILD_INT_MASK 0xf
|
|
#define PMU0_PLL0_PC2_WILD_INT_SHIFT 4
|
|
|
|
/* Chip specific PMU resources. */
|
|
#define RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
|
#define RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */
|
|
#define RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */
|
|
#define RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
|
#define RES4328_ILP_REQUEST 4 /* 0x00010 */
|
|
#define RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
|
#define RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
|
#define RES4328_ROM_SWITCH 7 /* 0x00080 */
|
|
#define RES4328_PA_REF_LDO 8 /* 0x00100 */
|
|
#define RES4328_RADIO_LDO 9 /* 0x00200 */
|
|
#define RES4328_AFE_LDO 10 /* 0x00400 */
|
|
#define RES4328_PLL_LDO 11 /* 0x00800 */
|
|
#define RES4328_BG_FILTBYP 12 /* 0x01000 */
|
|
#define RES4328_TX_FILTBYP 13 /* 0x02000 */
|
|
#define RES4328_RX_FILTBYP 14 /* 0x04000 */
|
|
#define RES4328_XTAL_PU 15 /* 0x08000 */
|
|
#define RES4328_XTAL_EN 16 /* 0x10000 */
|
|
#define RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */
|
|
#define RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */
|
|
#define RES4328_BB_PLL_PU 19 /* 0x80000 */
|
|
|
|
#define RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */
|
|
#define RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */
|
|
#define RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */
|
|
#define RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */
|
|
#define RES5354_ILP_REQUEST 4 /* 0x00010 */
|
|
#define RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */
|
|
#define RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */
|
|
#define RES5354_ROM_SWITCH 7 /* 0x00080 */
|
|
#define RES5354_PA_REF_LDO 8 /* 0x00100 */
|
|
#define RES5354_RADIO_LDO 9 /* 0x00200 */
|
|
#define RES5354_AFE_LDO 10 /* 0x00400 */
|
|
#define RES5354_PLL_LDO 11 /* 0x00800 */
|
|
#define RES5354_BG_FILTBYP 12 /* 0x01000 */
|
|
#define RES5354_TX_FILTBYP 13 /* 0x02000 */
|
|
#define RES5354_RX_FILTBYP 14 /* 0x04000 */
|
|
#define RES5354_XTAL_PU 15 /* 0x08000 */
|
|
#define RES5354_XTAL_EN 16 /* 0x10000 */
|
|
#define RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */
|
|
#define RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */
|
|
#define RES5354_BB_PLL_PU 19 /* 0x80000 */
|
|
|
|
/* pllcontrol registers */
|
|
/* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypsss_sdmod */
|
|
#define PMU1_PLL0_PLLCTL0 0
|
|
#define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000
|
|
#define PMU1_PLL0_PC0_P1DIV_SHIFT 20
|
|
#define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000
|
|
#define PMU1_PLL0_PC0_P2DIV_SHIFT 24
|
|
|
|
/* m<x>div */
|
|
#define PMU1_PLL0_PLLCTL1 1
|
|
#define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff
|
|
#define PMU1_PLL0_PC1_M1DIV_SHIFT 0
|
|
#define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00
|
|
#define PMU1_PLL0_PC1_M2DIV_SHIFT 8
|
|
#define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000
|
|
#define PMU1_PLL0_PC1_M3DIV_SHIFT 16
|
|
#define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000
|
|
#define PMU1_PLL0_PC1_M4DIV_SHIFT 24
|
|
|
|
/* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */
|
|
#define PMU1_PLL0_PLLCTL2 2
|
|
#define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff
|
|
#define PMU1_PLL0_PC2_M5DIV_SHIFT 0
|
|
#define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00
|
|
#define PMU1_PLL0_PC2_M6DIV_SHIFT 8
|
|
#define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000
|
|
#define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17
|
|
#define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000
|
|
#define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20
|
|
|
|
/* ndiv_frac */
|
|
#define PMU1_PLL0_PLLCTL3 3
|
|
#define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff
|
|
#define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0
|
|
|
|
/* pll_ctrl */
|
|
#define PMU1_PLL0_PLLCTL4 4
|
|
|
|
/* pll_ctrl, vco_rng, clkdrive_ch<x> */
|
|
#define PMU1_PLL0_PLLCTL5 5
|
|
#define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00
|
|
#define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8
|
|
|
|
#define RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */
|
|
#define RES4325_CBUCK_BURST 1 /* 0x00000002 */
|
|
#define RES4325_CBUCK_PWM 2 /* 0x00000004 */
|
|
#define RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */
|
|
#define RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */
|
|
#define RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */
|
|
#define RES4325_ILP_REQUEST 6 /* 0x00000040 */
|
|
#define RES4325_ABUCK_BURST 7 /* 0x00000080 */
|
|
#define RES4325_ABUCK_PWM 8 /* 0x00000100 */
|
|
#define RES4325_LNLDO1_PU 9 /* 0x00000200 */
|
|
#define RES4325_LNLDO2_PU 10 /* 0x00000400 */
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#define RES4325_LNLDO3_PU 11 /* 0x00000800 */
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#define RES4325_LNLDO4_PU 12 /* 0x00001000 */
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#define RES4325_XTAL_PU 13 /* 0x00002000 */
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#define RES4325_ALP_AVAIL 14 /* 0x00004000 */
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#define RES4325_RX_PWRSW_PU 15 /* 0x00008000 */
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#define RES4325_TX_PWRSW_PU 16 /* 0x00010000 */
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#define RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */
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#define RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */
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#define RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */
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#define RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */
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#define RES4325_HT_AVAIL 21 /* 0x00200000 */
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/* Chip specific ChipStatus register bits */
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#define CST4325_SPROM_OTP_SEL_MASK 0x00000003
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#define CST4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
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#define CST4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
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#define CST4325_OTP_SEL 2 /* OTP is powered up, no SPROM */
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#define CST4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */
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#define CST4325_SDIO_USB_MODE_MASK 0x00000004
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#define CST4325_SDIO_USB_MODE_SHIFT 2
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#define CST4325_RCAL_VALID_MASK 0x00000008
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#define CST4325_RCAL_VALID_SHIFT 3
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#define CST4325_RCAL_VALUE_MASK 0x000001f0
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#define CST4325_RCAL_VALUE_SHIFT 4
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#define CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */
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#define CST4325_PMUTOP_2B_SHIFT 9
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#define RES4312_SWITCHER_BURST 0 /* 0x00000001 */
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#define RES4312_SWITCHER_PWM 1 /* 0x00000002 */
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#define RES4312_PA_REF_LDO 2 /* 0x00000004 */
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#define RES4312_CORE_LDO_BURST 3 /* 0x00000008 */
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#define RES4312_CORE_LDO_PWM 4 /* 0x00000010 */
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#define RES4312_RADIO_LDO 5 /* 0x00000020 */
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#define RES4312_ILP_REQUEST 6 /* 0x00000040 */
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#define RES4312_BG_FILTBYP 7 /* 0x00000080 */
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#define RES4312_TX_FILTBYP 8 /* 0x00000100 */
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#define RES4312_RX_FILTBYP 9 /* 0x00000200 */
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#define RES4312_XTAL_PU 10 /* 0x00000400 */
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#define RES4312_ALP_AVAIL 11 /* 0x00000800 */
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#define RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */
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#define RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */
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#define RES4312_HT_AVAIL 14 /* 0x00004000 */
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/*
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* Maximum delay for the PMU state transition.
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* This is an upper bound intended for spinwaits etc.
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*/
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#define PMU_MAX_TRANSITION_DLY 15000
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#endif /* _SBCHIPC_H */
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