openwrt/target/linux/brcm47xx/patches-3.10/090-MIPS-BCM47XX-fix-clock-detection-for-BCM5354-with-20.patch

commit 0388a0410d590a6c239c1cfaa7d49bffd4ed1101
Author: Hauke Mehrtens <hauke@hauke-m.de>
Date:   Wed Sep 18 13:32:59 2013 +0200

    MIPS: BCM47XX: Fix clock detection for BCM5354 with 200MHz clock
    
    Some BCM5354 SoCs are running at 200MHz, but it is not possible to read
    the clock from a register like it is done on some other SoC in ssb and
    bcma. These devices should have a clkfreq nvram configuration value set
    to 200, read it and set the clock to the correct value.
    
    Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/5842/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

--- a/arch/mips/bcm47xx/time.c
+++ b/arch/mips/bcm47xx/time.c
@@ -27,10 +27,14 @@
 #include <linux/ssb/ssb.h>
 #include <asm/time.h>
 #include <bcm47xx.h>
+#include <bcm47xx_nvram.h>
 
 void __init plat_time_init(void)
 {
 	unsigned long hz = 0;
+	u16 chip_id = 0;
+	char buf[10];
+	int len;
 
 	/*
 	 * Use deterministic values for initial counter interrupt
@@ -43,15 +47,23 @@ void __init plat_time_init(void)
 #ifdef CONFIG_BCM47XX_SSB
 	case BCM47XX_BUS_TYPE_SSB:
 		hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
+		chip_id = bcm47xx_bus.ssb.chip_id;
 		break;
 #endif
 #ifdef CONFIG_BCM47XX_BCMA
 	case BCM47XX_BUS_TYPE_BCMA:
 		hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
+		chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
 		break;
 #endif
 	}
 
+	if (chip_id == 0x5354) {
+		len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
+		if (len >= 0 && !strncmp(buf, "200", 4))
+			hz = 100000000;
+	}
+
 	if (!hz)
 		hz = 100000000;